EDA課程設計：八路彩燈控制器

1、EDA課程設計設計題目：基于 VHDL的8路彩燈控制器設計一、課程設計的目的1 .熟悉Quartus U軟件的使用方法,使用VHDL文本輸入設計法進行任務設計。2增強自己實際動手能力，獨立解決問題的能力。3 .通過課程設計對所學的知識進行更新及鞏固.二、課程設計的基本要求本次課程設計是設計一個8路彩燈控制器，能夠控制8路彩燈按照兩種節(jié)拍， 三種花型循環(huán)變化。設計完成后，通過仿真驗證與設計要求進行對比， 檢驗設計 是否正確。三、課程設計的容編寫硬件描述語言VHDL程序，設計一個兩種節(jié)拍、三種花型循環(huán)變化的8路彩燈控制器，兩種節(jié)拍分別為 0.25s和0.5s。三種花型分別是：(1) 8路彩燈分成兩

2、半，從左至右順次漸漸點亮，全亮后則全滅。(2) 從中間到兩邊對稱地漸漸點亮，全亮后仍由中間向兩邊逐次熄滅。(3) 8路彩燈從左至右按次序依次點亮，全亮后逆次序依次熄滅。四、實驗環(huán)境PC 機一臺；軟件 Quartus n 6.0五、課程設計具體步驟及仿真結果1、系統總體設計框架結構fenpiri2:u1分頻模塊：把時鐘脈沖二分頻，得到另一個時鐘脈沖，讓這兩種時鐘脈沖來 交替控制花型的速度。二選一模塊：選擇兩種頻率中的一個控制彩燈的花型。8 路彩燈的三種花型控制模塊：整個系統的樞紐，顯示彩燈亮的情況2、系統硬件單元電路設計1.分頻模塊設計 實驗程序： library ieee;use ieee.s

3、td_logic_1164.all;entity fenpin2 isport( clk:in std_logic; clkk:out std_logic);end fenpin2;architecture behav of fenpin2 is beginprocess(clk)variable clkk1:std_logic:='0 beginclkk1:= not clkk1;if clk'event and clk='1' then end if;clkk<=clkk1;end process;end behav;RTL電路圖：波形圖：2.二選一模

4、塊設計 實驗程序： library ieee; use ieee.std_logic_1164.all; entity mux21 is port(a,b,s:in std_logic;y:out std_logic);end mux21;architecture behave of mux21 is beginprocess(a,b,s)beginif s='0' then y<=a;else y<=b;end if;end process;end behave;RTL電路圖：波形圖：3.8 路彩燈的三種花型控制模塊設計 程序: library ieee;use

5、ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity color8 is port(clk,rst :in std_logic;q:out std_logic_vector(7 downto 0); end;architecture a of color8 issignal s:std_logic_vector(4 downto 0); beginprocess(s,clk) beginif rst='1' then s<="00000"elsif clk'event a

6、nd clk= '1' thenif s="11111" then s<="00000"else s<=s+1; end if;case s iswhen "00000"=>q<="00000000"when "00001"=>q<="10001000"when "00010"=>q<="11001100"when "00011"=>q<=&

7、quot;11101110"when "00100"=>q<="11111111"when "00101"=>q<="00000000"when "00110"=>q<="00011000"when "00111"=>q<="00111100"when "01000"=>q<="01111110"when "01001

8、"=>q<="11111111"when "01010"=>q<="11100111"when "01011"=>q<="11000011"when "01100"=>q<="10000001"when "01101"=>q<="00000000"when "01110"=>q<="10000000&quo

9、t;when "01111"=>q<="11000000"when "10000"=>q<="11100000"when "10001"=>q<="11110000"when "10010"=>q<="11111000"when "10011"=>q<="11111100"when "10100"=>q<=

10、"11111110"when "10101"=>q<="11111111"when "10110"=>q<="11111110"when "10111"=>q<="11111100"when "11000"=>q<="11111000"when "11001"=>q<="11110000"when "1101

11、0"=>q<="11100000"when "11011"=>q<="11000000"when "11100"=>q<="10000000"when "11101"=>q<="00000000" when others=>null; end case;end if;end process; end;RTL電路圖：波形圖：4. 綜合程序 library ieee;use ieee.std_lo

12、gic_1164.all;entity fenpin2 isport( clk:in std_logic;clkk:out std_logic);end fenpin2;architecture behav of fenpin2 is beginprocess(clk)variable clkk1:std_logic:='0 beginclkk1:= not clkk1;if clk'event and clk='1' then end if;clkk<=clkk1;end process;end behav;library ieee;use ieee.s

13、td_logic_1164.all;entity mux21 isport(a,b,s:in std_logic;y:out std_logic);end mux21;architecture behave of mux21 is beginprocess(a,b,s)beginif s='0' then y<=a;else y<=b;end if;end process;end behave;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity color8

14、isport(clk,rst :in std_logic;q:out std_logic_vector(7 downto 0); end;architecture a of color8 is signal s:std_logic_vector(4 downto 0); begin process(s,clk) begin if rst='1' then s<="00000" elsif clk'event and clk= '1' then if s="11111" thens<="0000

15、0"else s<=s+1; end if; case s is when "00000"=>q<="00000000" when "00001"=>q<="10001000" when "00010"=>q<="11001100" when "00011"=>q<="11101110" when "00100"=>q<="1111

16、1111" when "00101"=>q<="00000000" when "00110"=>q<="00011000" when "00111"=>q<="00111100" when "01000"=>q<="01111110" when "01001"=>q<="11111111" when "01010&qu

17、ot;=>q<="11100111" when "01011"=>q<="11000011" when "01100"=>q<="10000001" when "01101"=>q<="00000000"when "01110"=>q<="10000000"when "01111"=>q<="11000000&quo

18、t;when "10000"=>q<="11100000"when "10001"=>q<="11110000"when "10010"=>q<="11111000"when "10011"=>q<="11111100"when "10100"=>q<="11111110"when "10101"=>q<=

19、"11111111"when "10110"=>q<="11111110"when "10111"=>q<="11111100"when "11000"=>q<="11111000"when "11001"=>q<="11110000"when "11010"=>q<="11100000"when "1101

20、1"=>q<="11000000"when "11100"=>q<="10000000"when "11101"=>q<="00000000"when others=>null;end case;end if;end process; end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity balucaideng isport (clk,s,rst:in std_logic;q:out std_logic_vector(7