北航電氣實(shí)驗(yàn)FPGA實(shí)驗(yàn)報(bào)告_第1頁(yè)
北航電氣實(shí)驗(yàn)FPGA實(shí)驗(yàn)報(bào)告_第2頁(yè)
北航電氣實(shí)驗(yàn)FPGA實(shí)驗(yàn)報(bào)告_第3頁(yè)
北航電氣實(shí)驗(yàn)FPGA實(shí)驗(yàn)報(bào)告_第4頁(yè)
北航電氣實(shí)驗(yàn)FPGA實(shí)驗(yàn)報(bào)告_第5頁(yè)
已閱讀5頁(yè),還剩7頁(yè)未讀, 繼續(xù)免費(fèi)閱讀

下載本文檔

版權(quán)說(shuō)明:本文檔由用戶提供并上傳,收益歸屬內(nèi)容提供方,若內(nèi)容存在侵權(quán),請(qǐng)進(jìn)行舉報(bào)或認(rèn)領(lǐng)

文檔簡(jiǎn)介

1、北京航空航天大學(xué)電氣實(shí)驗(yàn)報(bào)告FPGA實(shí)驗(yàn)張?zhí)?30325班 學(xué)號(hào):13031220一 實(shí)驗(yàn)?zāi)康穆远?實(shí)驗(yàn)要求略三 實(shí)驗(yàn)設(shè)備略四 實(shí)驗(yàn)內(nèi)容略五 實(shí)驗(yàn)實(shí)例1. 實(shí)例6-1思考題1:輸出信號(hào)q3q2q1綁定接口電路的七段數(shù)碼管或米字型數(shù)碼管或LED點(diǎn)陣顯示?答:思考題2:怎樣修改成4位二進(jìn)制減法計(jì)數(shù)器,具有清零,啟動(dòng)控制功能等?答:思考題3:把計(jì)數(shù)器修改成2位或更多位十進(jìn)制計(jì)數(shù)功能,再用七段數(shù)碼管進(jìn)行顯示等?答:2. 實(shí)例6-2思考題:一位半加器電路采用VHDL語(yǔ)言實(shí)驗(yàn) 答: library ieee;use ieee.std_logic_1164.all;use iee.std_logic_uns

2、igned.all;entity halfadd isport (a,b;in std_logicsum,carry; out std_logic)end entity halfadd;architecture halfadd isbeginsum<=a and(not b)+b and (not a);carry<= a and b;end architecture halfadd;六 實(shí)驗(yàn)過(guò)程我們組做的是一個(gè)利用led點(diǎn)陣規(guī)律亮滅變化形成字體,并且字體產(chǎn)生變化,形成“自動(dòng)化”的樣子,實(shí)現(xiàn)圖片如下圖:1. 實(shí)驗(yàn)分析:實(shí)驗(yàn)設(shè)計(jì)思路:本實(shí)驗(yàn)的設(shè)計(jì)思路是利用led燈的輝光效應(yīng),利用逐行

3、掃描,在高頻情況下就會(huì)顯示所有行的亮燈,進(jìn)而形成漢字,并且有時(shí)鐘計(jì)數(shù)程序,當(dāng)時(shí)鐘數(shù)字達(dá)到規(guī)定值(本實(shí)驗(yàn)為111111111b)時(shí),跳轉(zhuǎn)到下一個(gè)狀態(tài),顯示第二個(gè)憨子。每個(gè)漢字的顏色由led燈決定,改led矩陣有紅綠兩種led燈,因此有紅綠橙三種顏色顯示。2. 實(shí)現(xiàn)過(guò)程對(duì)設(shè)計(jì)思路的實(shí)現(xiàn)并非一帆風(fēng)順,最初編寫(xiě)的時(shí)候遇到了一些問(wèn)題。首先,定義輸入輸出角是個(gè)繁瑣的事情(需要定義40+次,每次必須手動(dòng)),另外,在程序編寫(xiě)過(guò)程中,也出現(xiàn)了一些邏輯錯(cuò)誤,對(duì)于錯(cuò)誤,我們仔細(xì)逐條語(yǔ)句分析,最終解決了錯(cuò)誤,解決過(guò)程中也加深了對(duì)FPGA的語(yǔ)言邏輯及硬件結(jié)構(gòu)的理解。七 .FPGA使用心得在學(xué)習(xí)FPGA過(guò)程中,我獲得了很

4、多收獲。首先,由于有單片機(jī)的基礎(chǔ),上手過(guò)程并不是十分復(fù)雜,對(duì)于輸入輸出的理解我沒(méi)有遇到太多阻礙。這次學(xué)習(xí)也驗(yàn)證了我具有短時(shí)間內(nèi)掌握一款新型的芯片的能力。學(xué)習(xí)過(guò)程中最大的困難就是VDHL語(yǔ)言的編寫(xiě)。我們以前有c語(yǔ)言的基礎(chǔ),不過(guò)學(xué)習(xí)這種新的語(yǔ)言還是花出了不少時(shí)間與精力,現(xiàn)在可以說(shuō)基本掌握的VDHL的基本寫(xiě)法和思路,能運(yùn)用到需要的程序中來(lái)。另外,調(diào)試的過(guò)程能極強(qiáng)地加大對(duì)程序的理解及邏輯的構(gòu)建,在調(diào)試中,逐漸明白了以前不懂的東西,對(duì)FPGA的工作原理的理解更加透徹了。不了解的人可能會(huì)把FPGA當(dāng)做一種單片機(jī),但其實(shí),相比于單片機(jī),F(xiàn)PGA是有很多優(yōu)勢(shì)的。其無(wú)固定的硬件結(jié)構(gòu)使其具有遠(yuǎn)超單片機(jī)的靈活性,另

5、外,它的編程方法可以同步進(jìn)行多個(gè)process使其能同步處理多個(gè)進(jìn)程,因此,它的運(yùn)算效率大大提高,在當(dāng)今社會(huì),有很大的利用價(jià)值。八 .電氣實(shí)驗(yàn)總結(jié)略附:程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity led isport(clk:in std_logic; rst:in std_logic; com:out std_logic_vector(7 downto 0); red:out std_logic_vector(7 downto 0); green:out std_logic

6、_vector(7 downto 0);end;architecture led of led isconstant s0:std_logic_vector(1 downto 0):="00" constant s1:std_logic_vector(1 downto 0):="01" constant s2:std_logic_vector(1 downto 0):="10" constant s3:std_logic_vector(1 downto 0):="11" signal present:std_log

7、ic_vector(1 downto 0); signal com1:std_logic_vector(7 downto 0);signal red1:std_logic_vector(7 downto 0);signal green1:std_logic_vector(7 downto 0);signal count:std_logic_vector(9 downto 0);signal zi:std_logic_vector(2 downto 0);beginprocess(rst,clk)beginif(rst='0')then-系統(tǒng)初始化 present<=s0;

8、 com1<=(others=>'0');elsif(clk'event and clk='1')then case present is when s0=>if(com1="00000000")then com1<="11111111" red1<="11111111" green1<="11111111" zi<="000" present<=s0; else if(count="1111111

9、11")then count<=(others=>'0'); present<=s1; else case zi is when "000"=> com1<="00001000" red1<="00000001" green1<="00000000" count<=count+1; zi<=zi+1; when "001" => com1<="00111100" red1<=&q

10、uot;00000010" green1<="00000000" count<=count+1; zi<=zi+1; when "010"=> com1<="00100100" red1<="00000100" green1<="00000000" count<=count+1; zi<=zi+1; when "011"=> com1<="00111100" red1<=&q

11、uot;00001000" green1<="00000000" count<=count+1; zi<=zi+1; when "100"=> com1<="00100100" red1<="00010000" green1<="00000000" count<=count+1; zi<=zi+1; when "101"=> com1<="00111100" red1<=&q

12、uot;00100000" green1<="00000000" count<=count+1; zi<=zi+1; when "110"=> com1<="00100100" red1<="01000000" green1<="00000000" count<=count+1; zi<=zi+1; when "111"=> com1<="00111100" red1<=&q

13、uot;10000000" green1<="00000000" count<=count+1; present<=s0; zi<="000" end case; end if; end if; when s1=>if(count="111111111")then -S1模式:從右到左逐個(gè)點(diǎn)亮LED count<=(others=>'0'); present<=s2; else present<=s1; case zi is when "000&

14、quot;=> com1<="00100000" red1<="00000001" green1<="00000001" count<=count+1; zi<=zi+1; when "001" => com1<="00100000" red1<="00000010" green1<="00000010" count<=count+1; zi<=zi+1; when "010

15、"=> com1<="00100110" red1<="00000100" green1<="00000100" count<=count+1; zi<=zi+1; when "011"=> com1<="11110000" red1<="00001000" green1<="00001000" count<=count+1; zi<=zi+1; when "100

16、"=> com1<="10101111" red1<="00010000" green1<="00010000" count<=count+1; zi<=zi+1; when "101"=> com1<="10100100" red1<="00100000" green1<="00100000" count<=count+1; zi<=zi+1; when "110

17、"=> com1<="10101010" red1<="01000000" green1<="01000000" count<=count+1; zi<=zi+1; when "111"=> com1<="10101111" red1<="10000000" green1<="10000000" count<=count+1; present<=s0; zi<=&quo

18、t;000" end case; count<=count+1; present<=s1; end if; when s2=>if(count="111111111")then -S2模式:從兩邊到中間逐個(gè)點(diǎn)亮LED count<=(others=>'0'); present<=s3; else case zi is when "000"=> com1<="00011000" red1<="00000000" green1<=&q

19、uot;00000001" count<=count+1; zi<=zi+1; when "001" => com1<="00010100" red1<="00000000" green1<="00000010" count<=count+1; zi<=zi+1; when "010"=> com1<="01010010" red1<="00000000" green1<=&

20、quot;00000100" count<=count+1; zi<=zi+1; when "011"=> com1<="00110011" red1<="00000000" green1<="00001000" count<=count+1; zi<=zi+1; when "100"=> com1<="00010010" red1<="00000000" green1<=&

21、quot;00010000" count<=count+1; zi<=zi+1; when "101"=> com1<="00011010" red1<="00000000" green1<="00100000" count<=count+1; zi<=zi+1; when "110"=> com1<="10010010" red1<="00000000" green1<=&

22、quot;01000000" count<=count+1; zi<=zi+1; when "111"=> com1<="11110010" red1<="00000000" green1<="10000000" count<=count+1; present<=s0; zi<="000" end case; count<=count+1; present<=s2; end if; when s3=>if(coun

23、t="111111111")then count<=(others=>'0'); present<=s0; else present<=s3; case zi is when "000"=> com1<="00000000" red1<="00000001" green1<="00000000" count<=count+1; zi<=zi+1; when "001" => com1<=&

24、quot;01100110" red1<="00000010" green1<="00000000" count<=count+1; zi<=zi+1; when "010"=> com1<="11111111" red1<="00000100" green1<="00000000" count<=count+1; zi<=zi+1; when "011"=> com1<="11111111" red1<="00001000" green1<=&

溫馨提示

  • 1. 本站所有資源如無(wú)特殊說(shuō)明,都需要本地電腦安裝OFFICE2007和PDF閱讀器。圖紙軟件為CAD,CAXA,PROE,UG,SolidWorks等.壓縮文件請(qǐng)下載最新的WinRAR軟件解壓。
  • 2. 本站的文檔不包含任何第三方提供的附件圖紙等,如果需要附件,請(qǐng)聯(lián)系上傳者。文件的所有權(quán)益歸上傳用戶所有。
  • 3. 本站RAR壓縮包中若帶圖紙,網(wǎng)頁(yè)內(nèi)容里面會(huì)有圖紙預(yù)覽,若沒(méi)有圖紙預(yù)覽就沒(méi)有圖紙。
  • 4. 未經(jīng)權(quán)益所有人同意不得將文件中的內(nèi)容挪作商業(yè)或盈利用途。
  • 5. 人人文庫(kù)網(wǎng)僅提供信息存儲(chǔ)空間,僅對(duì)用戶上傳內(nèi)容的表現(xiàn)方式做保護(hù)處理,對(duì)用戶上傳分享的文檔內(nèi)容本身不做任何修改或編輯,并不能對(duì)任何下載內(nèi)容負(fù)責(zé)。
  • 6. 下載文件中如有侵權(quán)或不適當(dāng)內(nèi)容,請(qǐng)與我們聯(lián)系,我們立即糾正。
  • 7. 本站不保證下載資源的準(zhǔn)確性、安全性和完整性, 同時(shí)也不承擔(dān)用戶因使用這些下載資源對(duì)自己和他人造成任何形式的傷害或損失。

評(píng)論

0/150

提交評(píng)論