S3C2410A通用異步收發(fā)報(bào)機(jī)(UART提供了三種獨(dú)立的異步.

1、摘要S3C2410A 通用異步收發(fā)報(bào)機(jī)(UART 提供了三種獨(dú)立的異步序列I/O (SIO)端口,每種都可以進(jìn)行基于中斷或基于直接存儲(chǔ)器存取(DMA 操作，也就是說，UART 可以在 CPU 和 UART間產(chǎn)生一個(gè)中斷或是 DMA 青求來傳送數(shù)據(jù)。使用系統(tǒng)計(jì)時(shí)器UART 可以將傳輸率提高到230.4K bps。如果給 UART 提供一個(gè)外部 UEXTCLK 裝置，那么 UART 可以以更快的速度運(yùn)行， 每個(gè) UART 通道包括 2 個(gè) 16 位 FIFOs 來接收或者發(fā)送。S3C2410A UART 功能包括可編程波特率，紅外收發(fā)，1 到 2 個(gè)停止位插入，5 位,6 位,7 位或 8 位帶寬

2、和奇偶效驗(yàn)。每個(gè) UART 包括一個(gè)波特率發(fā)生器 , 一個(gè)發(fā)射器 , 一個(gè)接受器和一組控制單元 ，如圖 111 所示，波特率發(fā)生器可以被 PCLK 或 UEXTCLK 計(jì)時(shí)。傳送器和接收器包括 16 位 FIFOs 和數(shù) 據(jù)開關(guān)，數(shù)據(jù)寫在 FIFO 上在傳送 前拷貝到傳送移位器上，然后這些數(shù)據(jù) 就被 TxDn 傳送 出去，同時(shí)，接收到的數(shù)據(jù)從 RxD n 中移出，從移位器上拷貝到 FIFO 上。特性-RxDO, TxD0, RxD1, TxD1, RxD2, 和 TxD2 都可以進(jìn)行基于中斷或基于DMA 操作-UART Ch 0, 1, and 2 with IrDA 1.0 & 16

3、-byte FIFO-UART Ch 0 and 1 with nRTS0, nCTS0, nRTS1, and nCTS1-支持握手接收和發(fā)送方框圖Penieral BUSTrafi&mitlerTransmit FIFO Rsg ster(FlFC TOds:Transmit BuflerR年卯鮒1令Byte)Transmit Shifter1ControlBuad-ratsUnit1GeneratorReceiverece .e Shiver一Transmit Holding RegisteriNori-FIFO modeC ock Source TXDnRscerve - ol

4、d ng Reg istei Ngn-IFO mode oniy)RXDnRscerve - old ng Reg istei Nan-FIFOmode only)Receive Fl=O eisteiReceive Fl=O eistei(FFOmode)er3ted.UART 錯(cuò)誤狀態(tài) FIFOUART 除有 Rx FIFO 寄存器.外還有錯(cuò)誤狀態(tài) FIFO,錯(cuò)誤狀態(tài) FIFO 表明在 FIFO registers 中，哪 個(gè)接收到的數(shù)據(jù)是錯(cuò)誤的，只有當(dāng)錯(cuò)誤的數(shù)據(jù)被讀出 時(shí)，錯(cuò)誤中斷才會(huì)停止。為人弄清錯(cuò) 誤狀態(tài) FIFO 有錯(cuò)誤的 URXH 和 UERSTAT 都要清除掉。例如:假如按順序

5、接收到字母 A.B.C.D.，當(dāng)只接收到 B 時(shí)就會(huì)發(fā)生幀錯(cuò)誤接收錯(cuò)誤不會(huì)產(chǎn)生任何錯(cuò) 誤中斷，因?yàn)榻邮盏降淖帜赣幸粋€(gè)錯(cuò)誤還沒被讀出 ，當(dāng)這個(gè)字母被讀出時(shí)就會(huì)產(chǎn)生錯(cuò)誤中 斷。圖 11-3 展示了 UART接收的四個(gè)特點(diǎn)包括一個(gè)錯(cuò)誤TimeSequence FlowError IntenuptNote#0When no diaracter is reod out#1A, B, C, artd D is receivedAfter A is read outThe frame error (in 6) inteatipt occurs.The B has to be read out.#3After

6、 B is read out#4After C is read out-#6After D is nead out圖 11-3 UART 接收的四個(gè)特點(diǎn)包括一個(gè)錯(cuò)誤Error Sistus-FIFOFrame Error-一-DCBRXHnUERSTATnError Status Gerteratof Unit1PRX-FIFO波特率的發(fā)生每個(gè) UART 勺波特率發(fā)生器提供連續(xù)的計(jì)時(shí)器給傳送器和接收器。波特率發(fā)生器的源時(shí)鐘可以由 S3C2410A 勺內(nèi)部系統(tǒng)時(shí)鐘或 UEXTCL 來選擇。換句話說，它被 UCON 的時(shí)鐘所選擇.波特率 時(shí)鐘是由源時(shí)鐘(PCLK 或 UEXTCLK 通過 UART

7、 勺差分波特率寄存器產(chǎn)生的(UBRDIVn)。通過以下方式UBRDIV 可以確定UBRDIVn = (int)(PCLK/(bps x 16) ) -1這里除數(shù)應(yīng)該從 1 到(216-1).為了使 UAR 精確的運(yùn)行，S3C2410A 也支持 UEXTCL 為被除數(shù)。如果 S3C2410A 用 UAR外卜部裝置或系統(tǒng)提供的 UEXTCLK 那么 UAR中的連續(xù)計(jì)時(shí)器就會(huì)和UEXTCL 保持同步。所以用戶可以獲得更精確的UAR 操作，UBRDIV 可以被確定為：UBRDI Vn = (i nt)(UEXTCLK / (bps x 16) )- 1這里， 除數(shù)應(yīng)該從 1 到(216-1)， 而且應(yīng)

8、該比 PCLK.小。 例如波特率為 115200 bps 而 PCLK 或 UEXTCLKis 40 MHz, UBRDIVn 取決于：UBRDIVn = (int)(40000000/(115200 x 16) -1= (int)(21.7) -1= 21 -1 = 20波特率錯(cuò)誤容差UART 幀錯(cuò)誤應(yīng)該少于 1.87%(3/160).tUPCLK = (UBRDIVn + 1) x 16 x 1幀/ PCLK tUPCLK :實(shí)際 UART 寸鐘tUEXACT = 1 幀/波特率 tUEXACT :理想 UART 寸鐘UART 錯(cuò)誤=(tUPCLK - tUEXACT) / tUEXACT

9、 x 100%1. 1 幀 = 起始位 + 數(shù)據(jù)位 + 效驗(yàn)位 + 停止位2. 在特殊情況下，我們可以將波特率提高到921.6K bps，例如，當(dāng) PCL 為 60MHz,時(shí)，你可以用 921.6K bps 的波特率而錯(cuò)誤小于 1.69%.循環(huán)模式S3C2410A UART!供一個(gè)測(cè)試模式，其中就包括循環(huán)模式，以解決通信中的孤立錯(cuò)誤。這種模式在結(jié)構(gòu)上給 UAR中的 RX 或 TXD 賦予聯(lián)系。主種允許處理器擴(kuò)大內(nèi)部傳送和接收每個(gè)SIO通道的數(shù)據(jù)路徑。這種模式可以通過在控制寄存器中設(shè)置循環(huán)位(UCON n 來選擇。紅外模式S3C2410A UAR 模塊支持紅外接收和發(fā)送，可以由UAR 線性控制寄

10、存器中的紅外模式設(shè)置位選擇（ULCONn。圖 11-4 顯示了紅外模式的執(zhí)行。 在紅外發(fā)送模式，發(fā)射信號(hào)脈沖由 3/16 的速率發(fā)出，以普通的序列發(fā)射速率（當(dāng)發(fā)射數(shù)據(jù)位為零）；在紅外接收模式，接收器必須檢測(cè)到 3/16的脈沖周期以識(shí)別出零電平（從圖 11-6 和 11-7 的時(shí)間圖可以看出）。圖 11-4 紅外模式方框圖圖 11-5 串行輸入/輸出幀時(shí)序圖（普通 UART4- IR Transrnit Frame- S0taiBit:Y1013D2naBarts113IStopBit1BitTime-斗一Pulse Width - 3H6 Bit Frame圖 11-6 紅外線傳輸模式幀時(shí)序圖

11、圖 11-7 紅外線接受模式幀時(shí)序圖UART 特殊寄存器UART 線性控制寄存器在 UART 模塊中有三組線性控制寄存器，包括ULCONO, ULC0N1,和 ULC0N2RegisterAddressR/WDescriplionReset ValueULCONO0 x5(X)00000UART channel 0 line control register0 x00ULCQN10 x50004000R/WUART channel 1 line control register0 x00ULC0N20 x5(X)08000UART channel 2 line control register

12、0 x00ULCONnBitDescriptionInitial StateReservedPlQInfra-Red ModenDetermine w+iether or not to use the Infra-Red mode.0 = Nonnal mode operation1 = Infra-Red Tx/Rx mode0Parity Mode5：3Specify the lype of parity generation and diecking during UART trnnniand recaiv operaijon.Oxx = No parity100 = Odd parit

13、y101 = Even parity110 = Parity forced/checked as 1111 = Parity forcedfehecked as 0000Number of Stop BitSpecify hw many stop bits are to be used for end-of-franie signal.0 = One stop bit per frame1 = Two stop bit per frame0Word Lertgiti1101Indicate the nuniber of daLa bits to be transnnitt總d or reciv

14、d perframe.00 = S4t01 =10 = 7-ht11 =00UAR 控制寄存器在 UART 模塊中有三組控制寄存器，包括UCONO, UCON 和 UCON2RegisterAddressR/WDescriptionReset ValueUCONC0 x50000004R?譏UART channel C contr-ol register0 x00UCON10 x50004004R?訓(xùn)UART channel 1 contr-ol register0 x00UCON20 x50008004UART channel 2 control register0 x00UCONnBitD

15、escriptionInitial StateClock Seledior(10Select PCLK or UEXTCLK for the UART baud rte.0-PCLK : UBRDIVn = (mtXPCLK/(bpsK16)-11=UEXTCLK(GPH6): UBRDIVn = (intXEXTCLK / (bps x 16) ) -10Tx Imtemjpt TypePlIntemipt request type.C = Pulse (Interrupt is requested soon as the Tx buffer becomes empty inNon-FIFO

16、 mode or reaches Tx FIFO Trigger L&vel m FIFO mode.)1 = Level (Interrupt叵requested while Tx buffer is empty in Non-FIFO mode wreaches Tx FIFO Trigger Level in FIFO mode.)0Rx Interrupt Type圈Intemipt nequesl type.0 = Pulse (Interrupt isthe instant Rx buffer receives thedata in Non-FIFO mode or rea

17、dies RKFIFO Trigger Level泊FIFO mode.)1 = Level (Interrupt is requested while Rx buffer is receiving data in Non-FIFOmode or reaches Rx FIFO Trigger Leve in FIFO mode )0Rx Time Otit EnableEnable/Disable Rx time out interrupt when UART FIFO is enabled. Theinterrupt is a receive interrupt0 = Disable1 =

18、 Enable0Rx Error SlatusInterrupt Enable問Enable the UART to generate an interrupt upon an exception, such as a frameerror, or overruri error during a receive operaticwi.0 = Do not generate recei ve error status interrupt.1 = Generate receive error status interrupt.0Loopback Mode問Setting kxipback bit

19、to 1 causes the UART to enter the loopback made. Thismode is provided for test purposes only.0 = Normal operationl = Loopback mode0Reserved4Reserved0UART 控制寄存器（連續(xù)）UCONnBitDescri ptionInitial StateTransmit Mode陽Determine which functwri is currently able to write Tx data to the UARTtransmit buffer reg

20、ister. (UART Tx Enable/Disable 00 = Disable01 = Intenupt request or polling mode10 = DMAOequesl (Only for UARTO).DMA3 request (Only for UART2)11 = DMA1 request Only for UART1)00Receive ModeHODetermine which functian i$ currentlyio read data from UARTreceive buffer r&gster. (UART Rx Enable.Disabl

21、ej00 - Disable01 = Interrupt requ&sl or polling nod&10 = DMA0 request (Only for UART0),DMAJ request (Only for UART2)11 = DMA1 request (Only for UART 1)00注意：當(dāng) UAR 在 DMA 接收模式中沒有達(dá)到 FIFO 觸發(fā)狀態(tài)而且沒有在 3 個(gè)字的時(shí)間內(nèi)接收到數(shù) 據(jù)，就會(huì)產(chǎn)生 Rx 中斷（接收超時(shí)），使用者就需要檢查FIFO 狀態(tài)和重置接收器。UART FIFO 控制寄存器在 UART 模塊中有三組 FIFO 控制寄存器，包括 UF

22、CONO, UFCON1 和 UFCON2RegisterAddressR/WDescriptionReset ValueUFCONOoxsooocooaR/WUART channel 0 FIFO comrol rei恥r0 x0UFCON10 x50004000R/WUART channel 1 FIFO conirol regisUrQMOUFCON2OxBOOO&DOBRJWUART channel 2 FIFO control register0 x0UFCONnBitDescriptionInitial StateTx FIFO Trigger Level陰Determin

23、e the trigger level of transmit FIFO. 00 = Empty01 =4-byte10 = 8-byte11 = 12-byte00Rx FIFO Trigger Level54Determine the trigger level of recere FIFO. 00 = 4-byte01 =8-byie10 = 12-b/te11 = 16-byte00Reserved同0Tx FIFO Reset2Airto-cleared after resetting FIFO0 = Normal仁Tx FIFO reset0Rx FIFO Reset1)Auio-

24、cleared after resetting FIFO0 = Mormal1= Rx FIFO reset0FIFO Enable00 = Disable1 = Enable0注意：當(dāng) UAR 在 DMA 接收模式中沒有達(dá)到 FIFO 觸發(fā)狀態(tài)而且沒有在 3 個(gè)字的時(shí)間內(nèi)接收到數(shù) 據(jù)，就會(huì)產(chǎn)生 Rx 中斷（接收超時(shí)），使用者就需要檢查FIFO 狀態(tài)和重置接收器。UART 調(diào)制解調(diào)控制寄存器在 UART 模塊中有兩組調(diào)制解調(diào)控制寄存器，包括UMCONO UMCON1RegisterAddressR/WDescriplionReset ValueUMCONOOxBOOOOOOCRA/VUART

25、chann建I Modem control register0 x0UMCON1Dx500040(JCRJWUART channel 1 Modem control register0 x0ReservedOxBOOOBOOC-ReservedUndefUMCONnBitDescriptionInitial StateReservedF：5These bits must be 0s00Auto Flow Control (AFC)40 = D3bl甘1 = Enable0Reserved陽These bits must be 0s00Request to Send0If AFC bit is

26、enabled, this value；vill be ignored. In this case theS3C24 IDA will control nRTS automatically.AFC bit i& disabled, nRTS must be controlled by software. 0 = Hlevel Inactivate nRTS)1 = V level (Activate nRTS)0注意：UART 2 不支持 AF（功能，因?yàn)?S3C2410A 沒有 nRTS2 和 nCTS2 寄存器。UART TX/RX 犬態(tài)寄存器在 UART 模塊中有三組 TX/RX

27、 狀態(tài)控制寄存器，包括 UTRSTATO, UTRSTAT1 和 UTRSTAT2RegisterAddressRWDescriptionReset ValueJTRSTATO0 x50000010RUART channel 0 Tx/Rx status register0 x6ITTRSTAT10 x50004010RUART channel 1 Tx/Rx status register0 x6LTTRSTAT20 x50000010RUART channel 2 TX/RKstatus registerUTRSTATnBitDescriptionInitial StateTransmit

28、ter emptyRSet to 1 automatically hen the transmit buffer register has no validdata io transnni and the Iransmit shift register is empty.0 = Not empty1 = Transmilter (transmii buffer i時(shí)register) empty1Transmit buffer emptySet to 1 automatically when transmit buffer register is empty.Q =The buffer reg

29、ister也not Empty1 = Empty(In Non-FIFO mode, Irtenupt or DMA is requested.In FIFO mode, Intmmjpl or DMA is requested, when Tx FIFOTrigger Level is set to 00 (Empty)If the HART uses the FIFQrusers should check Tx FIFO Count bitsand Tx FIFO Full bit in the UFSTAT register instead of this bit.1Receive bu

30、ffer data ready0Set to 1 aulomatically whenever receive buffer register contains validdata, received over the RXDn port0 = Empty1 = The buffer register has a received data(In Non-FIFO mode. Interrupt or DMA is requested)Jf the HART uses the FIFO, users should dieck Rx FIFO Count bit客and Rx FIFO Full

31、 bit in the UFSTAT register instead of this bit.0UART 錯(cuò)誤狀態(tài)寄存器在 UART 模塊中有三組錯(cuò)誤狀態(tài)寄存器，包括 UERSTATO, UERSTAT1 和 UERSTAT2RegisterAddressR/WDescriptionReset ValueUERSTAT00 x50000011RUART chartrtel 0 Rx error status register0 x0UERSTAT10 x50004014RUART channel 1 Rx error status register0 x0UERSTAT2Ox50008C14

32、RUART channel 2 Rx error status register0 x0UERSTATnBitDescriptionInitial StateReserved0 = No frame error during receive1 = Frame error (Intenupt is requested.)0Frame ErrorRSet to 1 autoniatically /whenever a frame error occurs during recerveoperation. = hto frame error dunng receive1 = Frame error (Interrupt is requested j0Reser/edDI0 = No frame error during receive1 = Frame error (Interrupt is requested.)0Ovefwn Error|0JSet to 1 auto