畢業(yè)設(shè)計方案說明書外文文獻及翻譯

1、外文文獻：Embedded Systems Design using the TI MSP430 Series up to larger (60k ROM, 2k RAM, with prices in the $10range devices. Currently, there are at least 40 flavors available, with more being added regularly. The devices are split into three families: the MSP430x3xx, which is a basic unit, the MSP43

2、0x1xx, which is a morefeature-rich family, and the MSP430x4xx, which is similar to the 1xx, witha built in LCD driver. You will find these referred to as 1xx, 3xx, and 4xxdevices throughout this book.Part Numbering ConventionPart numbers for MSP430 devices are determined based on their capabilities.

3、 All device part numbers follow the following template:MSP430M tFa F bMcM: Memory TypeC: ROMF: FlashP: OTPE: EPROM (for developmental use. There are few of these.F a, F b: Family and Features10, 11: Basic12, 13: Hardware UART14: Hardware UART, Hardware Multiplier31, 32: LCD Controller33: LCD Control

4、ler, Hardware UART, Hardware Multiplier41: LCD Controller43: LCD Controller, Hardware UART44: LCD Controller, Hardware UART, Hardware MultiplierMc: Memory Capacity0: 1kb ROM, 128b RAM1: 2kb ROM, 128b RAM2: 4kb ROM, 256b RAM3: 8kb ROM, 256b RAM4: 12kb ROM, 512b RAM5: 16kb ROM, 512b RAM6: 24kb ROM, 1k

5、b RAM7: 32kb ROM, 1kb RAM8: 48kb ROM, 2kb RAM9: 60kb ROM, 2kb RAMExample: The MSP430F435 is a Flash memory device with an LCDcontroller, a hardware UART, 16 kb of code memory, and 512 bytes of RAM.The part numbering scheme described above is a bit fragmented. Thereare common features not consistentl

6、y represented (type of ADC, number oftimers, etc, and there are some otherinconsistencies (for example, the 33family has the multiplier, but the 13 and 43s do not. I would recommendagainst selecting parts based on their numbering scheme. Rather, once youhave a vague idea of your requirements, go to

7、the TI website (www.TI.com,and use their parametric sort feature.Architecture: CPU and MemoryAs discussed in chapter 1, the MSP430 utilizes a 16-bit RISC architecture, which is capable of processing instructions on either bytes or words. TheCPU is identical for all members of the 430 family. It cons

8、ists of a 3-stageinstruction pipeline, instruction decoding, a 16-bit ALU, four dedicated-useregisters, and twelve working (or scratchpad registers. The CPU is connected to its memory through two 16-bit busses, one for addressing, and theother for data. All memory, including RAM, ROM, information me

9、mory, special function registers, and peripheral registers are mapped into a single, contiguous address space.This architecture is unique for several reasons. First, the designers at Texas Instruments have left an awful lot of space for future development. Almost half the Status Register remains ava

10、ilable for future growth, roughly half of the peripheral register space is unused, and only six of the sixteen available special function registers are implemented.Second, there are plenty of working registers. After years of having one or two workingregisters, I greatly enjoyed my first experience

11、with the twelve 16-bit CPU scratchpads. Theprogramming style is slightly different, and can be much more efficient, especially in the hands of a programmer who knows how to use this feature to its fullest.Third, this architecture is deceptively straightforward. It is very flexible, and the addressin

12、g modes are more complicated than most other smallprocessors. But, beyond that, this architecture is simple, efficient and clean. There are twobusses, a single linear memory space, a rather vanilla processor core, and all peripherals are memory-mapped.CPU FeaturesThe ALUThe 430 processor includes a

13、pretty typical ALU (arithmetic logic unit. The ALU handlesaddition, subtraction, comparison and logical (AND, OR, XOR operations. ALU operationscan affect the overflow, zero, negative, and carry flags. The hardware multiplier, which is notavailable in all devices, is implemented as a peripheral devi

14、ce, and is not part of the ALU (seeChapter 6.Working RegistersThe 430 gives the developer twelve 16-bit working registers, R4 through R15. (R0 through R3 are used for other functions, as described later. They are used for register mode operations (see Addressing Modes, Chapter 8, which are much more

15、 efficient than operations which require memory access. Some guidelines for their use:Use these registers as much as possible. Any variable which is accessed often shouldreside in one of these locations, for the sake of efficiency.Generally speaking, you may select any of these registers for any pur

16、pose, either dataor address. However, some development tools will reserve R4 and R5 for debuginformation. Different compilers will use these registers in different fashions, as well.Understand your tools.Be consistent about use of the working registers. Clearly document their use. I havecode, writte

17、n about 8 months ago, that performs extensive operations on R8, R9, andR15. Unfortunately, I dont know today what the values in R8, R9 and R15 represent.This was code I wrote to quickly validate an algorithm, rather than production code, so Ididnt document it sufficiently. Now, it is relative gibber

18、ish. Dont let this happen to you.No matter how obvious or trivial register use seems, document it anyway.Constant GeneratorsR2 and R3 function as constant generators, so that register mode may be used instead ofimmediate mode for some common constants. (R2 is a dualuse register. It serves as the Sta

19、tus Register, as well. Generated constants include some common single-bit values (0001h, 0002h, 0004h, and 0008h, zero (0000h, and an all 1s field (0FFFFh. Generation is based on the W(S value in the instruction word, and is described by the table below.W(S value in R2 value in R300 0000h01(0 (absol

20、ute mode0001h100004h0002h11 0008h 0FFFFhProgram CounterThe Program Counter is located in R0. Since individual memory location addresses are 8-bit, but all instructions are 16 bit, the PC is constrained to even numbers (i.e. the LSB of the PC is always zero. Generally speaking, it is best to avoid di

21、rect manipulation of the PC. One exception to this rule of thumb is the implementation of a switch, where the codejumps to a spot, dependent on a given value. (I.e., if value=0, jump to location0, if value=1,jump to location1, etc. This process is shown in Example 3.1.Example 3.1 Switch Statement vi

22、a Manual PC ControlMov value,R15 。put the switch value into R15Cmp R15,#8。 range checkingJge outofrange 。 if R157,do not use PC switchCmp #0,R15。 more range checkingJn outofrange 。Rla R15。 multiply R15 by two,since PC is always evenRla R15。 double R15again,sincesymbolic jmp is 2 words longAdd R15,PC

23、 。 PC goes to proper jumpJmp value0Jmp value1Jmp value2Jmp value3Jmp value4Jmp value5Jmp value6Jmp value7OutofrangeJmp RangeErrorThis is a relatively common approach, and most C compilers will implement switch statements with something similar. When implementing this manually (i.e., in assembly lang

24、uage, the programmer needs to keep several things in mind:Always do proper range checking. In the example, we checked for conditionsoutside both ends of the valid range. If this is not performed correctly, the code canjump to an unintended location.Pay close attention to the addressing modes of the

25、jump statements. The second doubling of R15, prior to the add statement, is added because the jump statement requires two words when symbolic mode addressing is used.Be careful that none of your interrupt handlers have the potential to affect your value register (R15 in the example. If the interrupt

26、 handler needs to use one of these registers, the handler needs to store the value to RAM first. The most common procedure is to push the register to the stack at the beginning of the ISR, and to pop the register at the end of the ISR. (See Example 3.2.Example 3.2 Push/Pop Combination in ISRTimer_A_

27、Hi_InterruptPush R12。 We will use R12Mov P1IN,R12 。 use R12 as we pleaseRla R12Rla R12Mov R12&BAR 。 Done with R12Pop R12。 Restore previous value to R12Reti。 return from interruptORG 0FFF0hDW Timer_A_Hi_InterruptStatus RegisterThe Status Register is implemented in R2, and is comprised of various syst

28、em flags. The flags are all directly accessible by code, and all but three of them are changed automatically by the processor itself. The 7 most significant bits are undefined. The bits of the SR are:?The Carry Flag (CLocation: SR(0 (the LSBFunction: Identifies when an operation results in a carry.

29、Can be set or cleared by software, or automatically.1=Carry occurred0=No carry occurred?The Zero Flag (ZLocation: SR(1Function: Identifies when an operation results in a zero. Can be set or cleared by software, or automatically.1=Zero result occurred0=Nonzero result occurred?The Negative Flag (NLoca

30、tion: SR(2Function: Identifies when an operation results in a negative. Can be set or cleared by software, or automatically. This flag reflects the value of the MSB of the operation result (Bit 7 for byte operations, and bit15 for word operations.1=Negative result occurred0=Positive result occurred?

31、The Global Interrupt Enable (GIELocation: SR(3Function: Enables or disables all maskable interrupts. Can be set or cleared by software, or automatically. Interrupts automatically reset this bit, and the reti instruction automatically sets it.1=Interrupts Enabled0=Interrupts Disabled?The CPU off bit

32、(CPUOffLocation: SR(4Function: Enables or disables the CPU core. Can be cleared by software, and is reset by enabled interrupts. None of the memory, peripherals, or clocks are affected by this bit. This bit is used as a power saving feature.1=CPU is on 0=CPU is off?The Oscillator off bit (OSCOffLoca

33、tion: SR(5Function: Enables or disables the crystal oscillator circuit (LFXT1. Can be cleared by software, and is reset by enabled external interrupts. OSCOff shuts down everything, including peripherals. RAM and register contents are preserved. This bit is used as a power saving feature.1=LFXT1 is

34、on0=LFXT1 is off?The System Clock Generator (SCG1,SCG0Location: SR(7,SR(6Function: These bits, along with OSCOff and CPUOff define the power mode of the device.?The Overflow Flag (VLocation: SR(8Function: Identifies when an operation results in an overflow. Can be set or cleared by software, or auto

35、matically. Overflow occurs when two positive numbers are added together, and the result is negative, or when two negative numbers are added together, and the result is positive.1=Overflow result occurred0=No overflow result occurredFour of these flags (Overflow, Negative, Carry, and Zero drive progr

36、am control, via instructions such as cmp (compare and jz (jump if Zero flag is set. You will see these flags referred to often in this book, as their function represents a fundamental building block. The instruction set is detailed in Chapter 9, and each base instruction description there details th

37、e interaction between flags and instructions. As a programmer, you need to understand this interaction.Stack PointerThe Stack Pointer is implemented in R1. Like the Program Counter, the LSB is fixed as a zero value, so the value is always even. The stack is implemented in RAM, and it is common pract

38、ice to start the SP at the top (highest valid value of RAM. The push command moves the SP down one word in RAM (SP=SP-2, and puts the value to be pushed at the new SP. Pop does the reverse. Call statements and interrupts push the PC, and ret and reti statements pop the value from the TOS (top of sta

39、ck back into the PC. I have one simple rule of thumb for the SP: leave it alone. Set the stack pointer as part of your initialization, and dont fiddle with it manually after that. As long as you are wary of two stack conditions, the stack pointermanages itself. These two conditions are:Asymmetric pu

40、sh/pop combinations. Every push should have a pop. If you push a bunch of variables, and fail to pop them back out, it will come back to haunt you. If you pop an empty stack, the SP moves out of RAM, and the program will fail.Stack encroachment. Remember, the stack is implemented in RAM. If your pro

41、gram has multiple interrupts, subroutine calls, or manual pushes, the stack will take up more RAM, potentially overwriting values your code needs elsewhere.Memory StructureSpecial Function RegistersSpecial function registers are, as you might have guessed,memory-mapped registers with special dedicat

42、ed functions. There are, nominally, sixteen of these registers, at memory locations 0000h through 000Fh. However, only the first six are used. Locations 0000h and 0001h contain interrupt enables, and locations 0002h and 0003h contain interrupt flags. These are described in Chapter 3.Locations 0004h

43、and 0005h contain module enable flags. Currently, only two bits are implemented in each byte. These bits are used for the USARTs.Peripheral RegistersAll on-chip peripheral registers are mapped into memory, immediately after the special function registers. There are two types of peripheral registers:

44、 byte-addressable, which are mapped in the space from 010h to 0FFh, and word-addressable, which are mapped from 0100h to 01FFh.RAMRAM always begins at location 0200h, and is contiguous up to its final address. RAM is used for all scratchpad variables, global variables, and the stack. Some rules of t

45、humb for RAM usage:The developer needs to be careful that scratchpad allocation and stack usage do not encroach on each other, or on global variables. Accidental sharing of RAM is a very common bug, and can be difficult to chase down. You need to clearly understand how large your stack will become.B

46、e consistent about use. Locate the stack at the very end of the RAM space, and place your most commonly used globals at the beginning.Never allocate more scratchpad than you need, and always deallocate as quickly as is reasonable. You can never have too much free RAM.Boot Memory (flash devices onlyB

47、oot memory is implemented in flash devices only, located in memory locations 0C00h through 0FFFh. It is the only hard-coded ROM space in the flash devices. This memory contains the bootstrap loader, which is used for programming of flash blocks, via a USART module.Information Memory (flash devices o

48、nlyFlash devices in the 430 family have the added feature of information memory. This information memory acts as onboard EEPROM, allowing critical variables to be preserved through power down. It is divided into two 128-byte segments.The first of these segments is located at addresses 01000h through

49、 0107Fh, and the second is at 01080h through 010FFh.Code MemoryCode memory is always contiguous at the end of the address space (i.e. always runs to location 0FFFFh. So, for 8k devices, code runs from 0E000h to 0FFFFh, and for the 60k devices, the code runs from 01100h to 0FFFFh. All code, tables, a

50、nd hard-coded constants reside in this memory space.Interrupt VectorsInterrupt vectors are located at the very end of memory space, in locations 0FFE0h through 0FFFEh. Programming and use of these are described in detail in Chapter 3.Memory TypesThe MSP430 is available with any one of several differ

51、ent memory types. The memory type is identified by the letter immediately following MSP430 in the part numbers. (Example: All MSP430Fxxx parts are flash decices.ROMROM devices, also known as masked devices, are identified by the letter C in the part nu mbers. They are strict ROM devices, shipped pre

52、-programmed. They have the adva ntage of being very in expe nsive, and may be the best soluti on for high-volume desig ns. However, due to high NRE (non-recurri ng engin eeri ng costs, masked ROM is on ly cost-efficie nt whe n hun dreds of thousa nds (or more devices are required. They should also o

53、nly be used for stable desig ns. If bugs are found too late in the process, the NRE costs have the potential to be repeated.OTPOTP is an acronym for one time programmable, which pretty well describes the functionality of these devices. Identified by the letter P in the part number, OTP parts are a g

54、ood compromise between ROM and flash parts. OTPs are shipped blank, and can be programmed at any time. They are typically more expensive than ROM. They also require program ming, which can be a hindrance in high-volume manu facturi ng en vir onmen ts. However, OTPs are ideal for low and medium volume applicati ons, and can be a usef