手冊stm8l參考手冊

1、RM0031Reference manualSTM8L15x microcontroller familyIntroductionThis reference manual targets application developers. It provides complete information on how to use the STM8L15x microcontroller memory and peripherals.The STM8L15x is a family of microcontrollers with different memory densities, pack

2、ages and peripherals.The medium-density STM8L15x devices are STM8L151x4, STM8L151x6, STM8L152x4, and STM8L152x6 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. They are designed for ultralow power applications.For ordering information, pin description, mechanical and

3、 electrical device characteristics, please refer to the STM8L15x datasheet.For information on the STM8 SWIM communication protocol and debug module, please refer to the user manual (UM0470).For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044).July 2010Doc ID 152

4、26 Rev 51/508ContentsRM0031Contents1 Central processing unit (CPU)271.1 Introduction271.2 CPU registers271.2.1 Description of CPU registers271.2.2 STM8 CPU register map311.3 Global configuration register (CFG_GCR)311.3.1 Activation level311.3.2 SWIM disable321.3.3 Description of global con

5、figuration register (CFG_GCR)321.3.4 Global configuration register map and reset values322 Boot ROM333 Flash program memory and data EEPROM (Flash)343.1 Introduction343.2 Glossary343.3 Flash main features353.4 Memory organization363.4.1 User boot area (UBC)363.4.2 Data EEPROM (DATA)373.4.3 Main prog

6、ram area383.4.4 Option bytes383.5 Memory protection383.5.1 Readout protection383.5.2 Memory access security system (MASS)383.5.3 Enabling write access to option bytes403.6 Memory programming403.6.1 Read-while-write (RWW)403.6.2 Byte programming403.6.3 Word programming413.6.4 Block programming423.6.5

7、 Option byte programming433.7 Flash low power modes432/508Doc ID 15226 Rev 5RM0031Contents3.8 ICP and IAP453.9 Flash registers463.9.1 Flash control register 1 (FLASH_CR1)463.9.2 Flash control register 2 (FLASH_CR2)483.9.3 Flash program memory unprotecting key register (FLASH_PUKR)493.9.4 Data EEPROM

8、 unprotection key register (FLASH_DUKR)493.9.5 Flash status register (FLASH_IAPSR)503.9.6 Flash register map and reset values514 Single wire interface module (SWIM) and debug module (DM)524.1 Introduction524.2 Main features524.3 SWIM modes525 Memory and register map535.1 Register description abbrevi

9、ations536 Power control (PWR)546.1 Power supply546.2 Power-on reset (POR)/power-down reset (PDR)556.3 Brownout reset (BOR)556.4 Programmable voltage detector (PVD)566.5 Voltage regulator576.6 PWR registers596.6.1 Power control and status register 1 (PWR_CSR1)596.6.2 PWR control and status register 2

10、 (PWR_CSR2)606.6.3 PWR register map and reset values607 Low power modes617.1 Slowing down the system clocks627.2 Peripheral clock gating (PCG)627.3 Wait mode (WFI or WFE mode)627.4 Wait for interrupt (WFI) mode637.5 Wait for event (WFE) mode637.5.1 WFE registers647.5.2 WFE register map and reset val

11、ues68Doc ID 15226 Rev 53/508ContentsRM00317.6 Low power run mode697.6.1 Entering Low power run mode697.6.2 Exiting Low power run mode697.7 Low power wait mode697.8 Halt mode707.8.1 Entering Halt mode707.8.2 Exiting Halt mode707.9 Active-halt mode718 Reset (RST)728.1 “Reset state” and “under reset” d

12、efinitions728.2 External reset (NRST pin)728.2.1 Asynchronous external reset description728.2.2 Configuring NRST/PA1 pin as general purpose output738.3 Internal reset738.3.1 Power-on reset (POR)738.3.2 Independent watchdog reset738.3.3 Window watchdog reset738.3.4 SWIM reset738.3.5 Illegal opcode re

13、set738.4 RST registers758.4.1 Reset pin configuration register (RST_CR)758.4.2 Reset status register (RST_SR)758.4.3 RST register map and reset values769 Clock control (CLK)779.1 Introduction779.2 HSE clock789.3 HSI clock799.4 LSE clock809.5 LSI clock809.6 System clock sources819.6.1 System startup8

14、19.6.2 System clock switching procedures819.7 Peripheral clock gating (PCG)839.8 Clock security system (CSS)844/508Doc ID 15226 Rev 5RM0031Contents9.8.1 Clock security system on HSE849.9 RTC and LCD clock859.10 BEEP clock859.11 Configurable clock output capability (CCO)859.12 Clock-independent syste

15、m clock sources for TIM2/TIM3869.13 CLK interrupts869.14 CLK registers869.14.1 System clock divider register (CLK_CKDIVR)869.14.2 Clock RTC register (CLK_CRTCR)889.14.3 Internal clock register (CLK_ICKCR)899.14.4 Peripheral clock gating register 1 (CLK_PCKENR1)909.14.5 Peripheral clock gating regist

16、er 2 (CLK_PCKENR2)919.14.6 Configurable clock output register (CLK_CCOR)929.14.7 External clock register (CLK_ECKCR)939.14.8 System clock status register (CLK_SCSR)949.14.9 System clock switch register (CLK_SWR)959.14.10 Switch control register (CLK_SWCR)959.14.11 Clock security system register (CLK

17、_CSSR)969.14.12 Clock BEEP register (CLK_CBEEPR)979.14.13 HSI calibration register (CLK_HSICALR)979.14.14 HSI clock calibration trimming register (CLK_HSITRIMR)989.14.15 HSI unlock register (CLK_HSIUNLCKR)989.14.16 Main regulator control status register (CLK_REGCSR)999.14.17 CLK register map and res

18、et values10010 General purpose I/O ports (GPIO)10110.1 Introduction10110.2 GPIO main features10110.3 Port configuration and usage10210.3.1 Input modes10410.3.2 Output modes10410.4 Reset configuration10410.5Unused I/O p. 10410.6 Low power modes10410.7 Input mode details10510.7.1 Alternate function in

19、put105Doc ID 15226 Rev 55/508ContentsRM003110.7.2Interrupt capability10510.8Outputmode details10510.8.1Alternate function output10510.8.2Slope control10510.9 GPIO registers10610.9.1 Port x output data register (Px_ODR)10610.9.2 Port x pin input register (Px_IDR)10610.9.3 Port x data direction regist

20、er (Px_DDR)10710.9.4 Port x control register 1 (Px_CR1)10710.9.5 Port x control register 2 (Px_CR2)10810.9.6 Peripheral alternate function remapping10810.9.7 GPIO register map and reset values10811 Routing interface (RI) and system configurationcontroller (SYSCFG)10911.1 Introduction10911.2 RI main

21、features10911.3 RI functional description11011.3.1 I/O groups11111.3.2 TIM1 input capture routing11211.3.3 Comparator routing11311.3.4 DAC routing11311.3.5 Internal reference voltage routing11411.4 RI registers11511.4.1 Timer input capture routing register 1 (RI_ICR1)11511.4.2 Timer input capture ro

22、uting register 2 (RI_ICR2)11511.4.3 I/O input register 1 (RI_IOIR1)11511.4.4 I/O input register 2 (RI_IOIR2)11611.4.5 I/O input register 3 (RI_IOIR3)11611.4.6 I/O control mode register 1 (RI_IOCMR1)11611.4.7 I/O control mode register 2 (RI_IOCMR2)11711.4.8 I/O control mode register 3 (RI_IOCMR3)1171

23、1.4.9 I/O switch register 1 (RI_IOSR1)11811.4.10 I/O switch register 2 (RI_IOSR2)11811.4.11 I/O switch register 3 (RI_IOSR3)11911.4.12 IO group control register (RI_IOGCR)11911.4.13 Analog switch register 1 (RI_ASCR1)1206/508Doc ID 15226 Rev 511.4.14 Analog switch register 2 (RI_ASCR2)12011.4.15 Res

24、istor control register (RI_RCR)12111.4.16 RI register map and reset values12211.5 SYSCFG registers12311.5.1 SYSCFG remap control register 1 (SYSCFG_RMPCR1)12311.5.2 SYSCFG remap control register 2 (SYSCFG_RMPCR2)12411.5.3 SYSCFG register map and reset values12412 Interrupt controller (ITC)12512.1 IT

25、C introduction12512.2 Interrupt masking and processing flow12512.2.1 Servicing pending interrupts12612.2.2 Interrupt sources12712.3 Interrupts and low power modes12812.4 Activation level/low power mode control12912.5 Concurrent and nested interrupt management12912.5.1 Concurrent interrupt management

26、 mode12912.5.2 Nested interrupt management mode13012.6 External interrupts13112.7 Interrupt tructions13212.8 Interrupt mapping13212.9 ITC and EXTI registers13312.9.1 CPU condition code register interrupt bits (CCR)13312.9.2 Software priority register x (ITC_SPRx)13412.9.3 External interrupt control

27、register 1 (EXTI_CR1)13512.9.4 External interrupt control register 2 (EXTI_CR2)13612.9.5 External interrupt control register 3 (EXTI_CR3)13712.9.6 External interrupt status register 1 (EXTI_SR1)13812.9.7 External interrupt status register 2 (EXTI_SR2)13912.9.8 External interrupt port select register

28、 (EXTI_CONF1)14012.9.9 ITC and EXTI register map and reset values14113 Direct memory access controller (DMA)14213.1 DMA introduction142Glossary14213.2 DMA main features142Doc ID 15226 Rev 57/50813.3 DMA functional description14313.3.1 DMA transactions14313.3.2 DMA arbiter14413.3.3 DMA channels14413.

29、3.4 DMA1 request mapping149DMA hardware request description15013.4 DMA low power modes15213.5 DMA interrupts15213.6 DMA registers15313.6.1 DMA global configuration & status register (DMA_GCSR)15313.6.2 DMA global interrupt register 1 (DMA_GIR1)15413.6.3 DMA channel configuration register (DMA_CxCR)1

30、5413.6.4 DMA channel status & priority register (DMA_CxSPR)15613.6.5 DMA number of data to transfer register (DMA_CxNDTR)15713.6.6 DMA peripheral address high register (DMA_CxPARH)15713.6.7 DMA peripheral address low register (DMA_CxPARL)15813.6.8 DMA channel 3 peripheral address high & memory 1 add

31、ress high register (DMA_C3PARH_C3M1ARH)15913.6.9 DMA channel 3 peripheral address low & memory 1 address lowregister (DMA_C3PARL_C3M1ARL)16013.6.10 DMA memory 0 address high register (DMA_CxM0ARH)16113.6.11 DMA memory 0 address low register (DMA_CxM0ARL)16113.6.12 DMA register map and reset values16

32、114 Analog-to-digital converter (ADC)16414.1 ADC introduction16414.2 ADC main features16414.3 ADC functional description16514.3.1 General description16514.3.2 Number of analog channels16614.3.3 ADC on-off control16614.3.4 Single conversion mode16614.3.5 Continuous conversion mode16814.3.6 ADC clock1

33、6814.3.7 Analog watchdog16814.3.8 Interrupts16814.3.9 Channel selection (Scan mode)1698/508Doc ID 15226 Rev 514.3.10 Data integrity17014.3.11 DMA transfer17014.3.12 Configurable resolution17014.3.13 Data alignment17014.3.14 Programmable sampling time17214.3.15 Schmitt trigger disabling17214.3.16 Tem

34、perature sensor17214.3.17 Internal reference voltage conversion17314.4 ADC low power modes17314.5 ADC interrupts17414.6 ADC registers17414.6.1 ADC configuration register 1 (ADC_CR1)17414.6.2 ADC configuration register 2 (ADC_CR2)17514.6.3 ADC configuration register 3 (ADC_CR3)17614.6.4 ADC status re

35、gister (ADC_SR)17714.6.5 ADC data register high (ADC_DRH)17814.6.6 ADC data register low (ADC_DRL)17814.6.7 ADC high threshold register high (ADC_HTRH)17914.6.8 ADC high threshold register low (ADC_HTRL)17914.6.9 ADC low threshold register high (ADC_LTRH)17914.6.10 ADC low threshold register low (AD

36、C_LTRL)18014.6.11 ADC channel sequence 1 register (ADC_SQR1)18014.6.12 ADC channel sequence register 2 (ADC_SQR2)18114.6.13 ADC channel select scan 3 (ADC_SQR3)18114.6.14 ADC channel select scan 4 (ADC_SQR4)18214.6.15 ADC trigger disable 1 (ADC_TRIGR1)18214.6.16 ADC trigger disable 2 (ADC_TRIGR2)183

37、14.6.17 ADC trigger disable 3 (ADC_TRIGR3)18314.6.18 ADC trigger disable 4 (ADC_TRIGR4)18314.6.19 ADC register map and reset values18415 Digital to analog converter (DAC)18515.1 DAC introduction18515.2 DAC main features18515.3 DAC functional description18615.3.1 DAC channel x enable18615.3.2 DAC out

38、put buffer enable186Doc ID 15226 Rev 59/508ContentsRM003115.3.3 DAC output switch configuration18615.3.4 DAC data format18615.3.5 DAC conversion sequence18715.3.6 DAC output voltage18715.3.7 DAC trigger selection18715.3.8 DAC DMA request18815.3.9 DAC DMA underrun interrupt18815.4 DAC registers18915.

39、4.1 DAC channel control register 1 (DAC_CR1)18915.4.2 DAC channel x control register 2 (DAC_CR2)19015.4.3 DAC software trigger register (DAC_SWTRIGR)19115.4.4 DAC status register (DAC_SR)19215.4.5 DAC right aligned data holding register high(DAC_RDHRH)19315.4.6 DAC right aligned data holding registe

40、r low(DAC_RDHRL)19315.4.7 DAC left aligned data holding register high(DAC_LDHRH)19415.4.8 DAC left aligned data holding register low(DAC_LDHRL)19415.4.9 DAC 8-bit data holding register(DAC_DHR8)19415.4.10 DAC channel x data output register high (DAC_DORH)19515.4.11 DAC data output register low(DAC_D

41、ORL)19515.4.12 DAC register map and reset values19516 Comparators (COMP)19716.1 COMP introduction19716.2 COMP main features19816.3 Comparator 1 (COMP1)19916.4 Comparator 2 (COMP2)20016.5 Using the comparators in window mode20116.6 COMP low power modes20216.7 COMP interrupts20216.8 COMP registers2031

42、6.8.1 Comparator control and status register 1 (COMP_CSR1)20316.8.2 Comparator control and status register 2 (COMP_CSR2)20410/508Doc ID 15226 Rev 5RM0031Contents16.8.3 Comparator control and status register 3 (COMP_CSR3)20516.8.4 Comparator control and status register 4 (COMP_CSR4)20616.8.5 Comparat

43、or control and status register 5 (COMP_CSR5)20616.8.6 COMP register map and reset values20717 LCD controller20817.1 LCD controller introduction20817.1.1 Definitions20817.2 LCD controller main features20917.3 LCD functional description21017.3.1 General description21017.3.2 Frequency generator21017.3.

44、3 Common driver21317.3.4 Segment driver21917.3.5 Enabling a segment22017.3.6 Blink22017.3.7 Generation of LCD voltage levels22017.4 LCD controller low power modes22217.5 LCD controller interrupts22217.6 LCD controller registers22317.6.1 Control register 1 (LCD_CR1)22317.6.2 Control register 2 (LCD_C

45、R2)22417.6.3 Control register 3 (LCD_CR3)22517.6.4 Frequency selection register (LCD_FRQ)22617.6.5 Port mask registers (LCD_PM)22617.6.6 LCD display memory (LCD_RAM)22717.6.7 LCD register map and reset values22818 Timer overview23018.1 Timer feature comparison23118.2 Glossary of timer signal names23

46、219 16-bit advanced control timer (TIM1)23419.1 Introduction23419.2 TIM1 main features23519.3 TIM1 time base unit237Doc ID 15226 Rev 511/508ContentsRM003119.3.1 Reading and writing to the 16-bit counter23819.3.2 Write sequence for 16-bit TIM1_ARR register23819.3.3 Prescaler23819.3.4 Up-counting mode

47、23919.3.5 Down-counting mode24119.3.6 Center-aligned mode (up/down counting)24319.3.7 Repetition down-counter24519.4 TIM1 clock/trigger controller24719.4.1 Prescaler clock (CK_PSC)24719.4.2 Internal clock source (fSYSCLK)24819.4.3 External clock source mode 124819.4.4 External clock source mode 2250

48、19.4.5 Trigger synchronization25119.4.6 Synchronization between timers25519.5 TIM1 capture/compare channels26119.5.1 Write sequence for 16-bit TIM1_CCRi registers26219.5.2 Input stage26319.5.3 Input capture mode26419.5.4 Output stage26619.5.5 Forced output mode26719.5.6 Output compare mode26719.5.7

49、PWM mode27019.5.8 Using the break function27719.5.9 Clearing the OCiREF signal on an external event28019.5.10 Encoder interface mode28119.5.11 Timer input XOR function28319.5.12 Interfacing with Hall sensors28319.6 TIM1 interrupts28519.6.1 TIM1 wait-for-event capability28519.7 TIM1 DMA28519.7.1 DMA

50、single mode28519.7.2 DMA burst mode28619.8 TIM1 registers28719.8.1 Control register 1 (TIM1_CR1)28719.8.2 Control register 2 (TIM1_CR2)28919.8.3 Slave mode control register (TIM1_SMCR)29019.8.4 External trigger register (TIM1_ETR)29112/508Doc ID 15226 Rev 5RM0031Contents19.8.5 DMA request enable reg

51、ister (TIM1_DER)29319.8.6 Interrupt enable register (TIM1_IER)29419.8.7 Status register 1 (TIM1_SR1)29519.8.8 Status register 2 (TIM1_SR2)29619.8.9 Event generation register (TIM1_EGR)29719.8.10 Capture/compare mode register 1 (TIM1_CCMR1)29819.8.11 Capture/compare mode register 2 (TIM1_CCMR2)30119.

52、8.12 Capture/compare mode register 3 (TIM1_CCMR3)30219.8.13 Capture/compare mode register 4 (TIM1_CCMR4)30319.8.14 Capture/compare enable register 1 (TIM1_CCER1)30419.8.15 Capture/compare enable register 2 (TIM1_CCER2)30719.8.16 Counter high (TIM1_CNTRH)30719.8.17 Counter low (TIM1_CNTRL)30819.8.18

53、Prescaler high (TIM1_PSCRH)30819.8.19 Prescaler low (TIM1_PSCRL)30819.8.20 Auto-reload register high (TIM1_ARRH)30919.8.21 Auto-reload register low (TIM1_ARRL)30919.8.22 Repetition counter register (TIM1_RCR)30919.8.23 Capture/compare register 1 high (TIM1_CCR1H)31019.8.24 Capture/compare register 1

54、 low (TIM1_CCR1L)31019.8.25 Capture/compare register 2 high (TIM1_CCR2H)31119.8.26 Capture/compare register 2 low (TIM1_CCR2L)31119.8.27 Capture/compare register 3 high (TIM1_CCR3H)31219.8.28 Capture/compare register 3 low (TIM1_CCR3L)31219.8.29 Capture/compare register 4 high (TIM1_CCR4H)31319.8.30 Capture/compare register 4 low (TIM1_CCR4L)31319.8.31 Break register (TIM1_BKR)31419.8.32 Deadtime register (TIM1_DTR)31519.8.33 Output idle state register (TIM1_OISR)31619.8.34 DMA control register 1 (TIM1_DCR1)31619.8.35 DMA control register 2 (TIM1_DCR2)317