外文翻譯--單片機(jī)工作原理

英文原文THEPRINCIPLEOFMICROCONTROLLERINOPERATIONTHESINGLECHIPMICROCOMPUTERSCMISCONNECTEDTOAHOSTPCMICROCOMPUTERVIAASERIALPORTTHECONNECTINGCABLEISINCLUDEDWITHTHEUNITTHESCMISSUPPLIEDFITTEDWITHAN8751CHIPTHISCHIPFEATURESINTERNALROMCONTAININGVERSATILE,REALTIMEMONITORTOCOMMUNICATEWITHAPCVIATHEBUILTINSERIALPORTTHEMONITORINCLUDESALINEASSEMBLER,DISASSEMBLER,BREAKPOINTS,SINGLESTEPPINGANDTHEFACILITYTOEXAMINEANDEXCHANGEMEMORYORREGISTERCONTENTSASPECIALFUNCTIONOFTHEMONITORISTOSTORETHEPROGRAMUNDERDEVELOPMENTINTHERAMOFTHESCMDEVELOPMENTBOARDTHEGREATADVANTAGEOFTHEMETHODTHATISDIRECTACCESSTOTHEI/OPORTSISPROVIDEDBYTHE8051ISRETAINEDAND,CONSEQUENTLY,THENEEDFORACOSTLYINCIRCUITEMULATIONICEPACKAGEISNOTREQUIREDONCEAPROGRAMHASBEENCOMPLETEDONTHESCMDEVELOPMENTSYSTEMITCANBEEASILYTRANSFERREDINTOTHEROMOFANOTHER8751VIAANEPROMPROGRAMMERTHISSECOND8751,NOWCONTAININGTHECONTROLPROGRAM,CANBEREMOVEDFROMTHEPROGRAMMERANDINSTALLEDINTOTHESCMTBTARGETBOARDMOSTIMPORTANTLY,BECAUSEDIRECTACCESSTOTHEINPUT/OUTPUTPORTSOFTHE8751HASBEENRETAINEDDURINGTHEDEVELOPMENTSTAGETHEREISNONEEDFORPERIPHERALI/OANDADDRESSDECODINGCHIPSONLYTHE8751CHIPISREQUIREDTHUSTHESINGLECHIPMICROCONTROL,NOTMULTICHIPCONTROLISREALISEDTHESCMTBTARGETBOARDFEATUREASINGLE40WAYDILSOCKETFORTHEMICROCONTROLLERCHIPPLUSTERMINATIONFACILITIESIDENTICALTOTHESCMDEVELOPMENTBOARDFORSIMPLEANDCONVENIENTTRANSFEROFANYCONNECTINGCABLES8751ICSSHOULDBEPURCHASEDSEPARATELYFORTHETARGETBOARDINADDITIONTOTHESINGLECHIPDEVELOPMENTSYSTEMANDTARGETBOARD,ANUMBEROFADDONBOARDSAREAVAILABLETHESEINCLUDEAPORTMONITORBOARD,MULTICHANNELADC,SCREWTERMINALBOARDANDOUTPUTDRIVERBOARDVOICEINPUTTOAMACHINEISTHEMOSTNATURALFORMOFMANMACHINECOMMUNICATIONSRESEARCHCOMINGTOFRUITIONOVERTHEPASTSEVERALYEARSINDICATESTHATTHETECHNIQUESOFMANMACHINECOMMUNICATIONBYVOICECONSTITUTEAWHOLENEWRANGEOFCOMMUNICATIONSERVICESSERVICESTHATCANEXTENDMANSCAPABILITIES,SERVEHISSOCIALNEEDS,ANDINCREASEHISPRODUCTIVITYSPEECHRECOGNITIONCANBEDEFINEDASTHETECHNOLOGYWHICHMAKESITPOSSIBLEFORACOMPUTERTOACCEPTVOICEDATAASINPUTANDTHENIDENTIFYTHEWORDORPHRASESTHEREISATWOFOLDRATIONALEFORASPEECHRECOGNITIONSYSTEA1ITISANEASIERMEANSFORNONCOMPUTERPROFESSIONALSTOENTERDATAINTOTHECOMPUTER2INCERTAINAPPLICATIONS,SUCHASINSEMIAUTOMATEDQUALITYCONTROLINSPECTIONPROCEDURES,COMPUTERUSERSNEEDTOUSETHEIRHANDSFOROTHERTASKSSPEECHRECOGNITIONISAPARTOFABROADERSPEECHPROCESSINGTECHNOLOGYINVOLVINGCOMPUTERIDENTIFICATIONORVERIFICATIONOFSPEAKERS,COMPUTERSYNTHESISOFSPEECH,PRODUCTIONOFSTOREDSPOKENRESPONSES,COMPUTERANALYSISOFTHEPHYSICALANDPSYCHOLOGICALSTATEOFTHESPEAKER,EFFICIENTTRANSMISSIONOFSPOKENCONVERSATIONS,DETECTIONOFSPEECHPATHOLOGIES,ANDAIDSTOTHEHANDICAPPED,TAKINGMACHINESTALKANDLISTENTOHUMANSDEPENDSUPONECONOMICALIMPLEMENTATIONOFSPEECHSYNTHESISANDSPEECHRECOGNITIONANUMBEROFDIFFERENTFEATURESETSHAVEBEENPROPOSEDTOREPRESENTSPEECHSIGNALSTHESEINCLUDEENERGYANDZEROCROSSINGRATES,FORMANTFILTERING,SHORTTIMESPECTRUM,WAVEFORMDIGITIZATIONANDLINEARPREDICTIVECODINGLPCTHEMOTIVATIONFORCHOOSINGONEFEATURESETOVERANOTHERISOFTENCOMPLEXANDHIGHLYDEPENDENTANCONSTRAINTSIMPOSEDUPONTHESYSTEM,EG,COST,SPEED,RESPONSETIME,COMPUTATIONALCOMPLEXITY,ETCOFALLTHEMANYAVAILABLEFEATURESETS,LINEARPREDICTIVECODINGISUSUALLYTHEMOSTEFFECTIVEONETHEREAREMANYCLASSIFICATIONSFORCOMPUTERS,RANGINGFROMINEXPENSIVEMICROCOMPUTERSUSEDINHOMESANDOFFICES,TOLIQUIDCOOLEDSUPERCOMPUTERSUSEDINUNIVERSITIESANDRESEARCHLABORATORIESTHEPRESENTINVENTIONRELATESTOMICROCOMPUTERS,ALSOKNOWNAS“PERSONALCOMPUTERS“OR“PCS“AMICROCOMPUTERCANBEDEFINEDASA“COMPUTERHAVINGAMASSPRODUCEDINTEGRATEDCIRCUITMICROPROCESSOR“,SUCHAS,FOREXAMPLE,THEINTEL8086FAMILYOFPRODUCTSWHICHPRESENTLYINCLUDESTHE8086,80286,80386AND80486MICROPROCESSORSALTHOUGHTHEMICROPROCESSORISTHEHEARTANDDEFININGFEATUREOFAMICROCOMPUTER,ITISNOTVERYUSEFULUNLESSITISINTEGRATEDWITHAMEMORYANDASETOFINPUT/OUTPUT“I/O“DEVICES,ALSOKNOWNASPERIPHERALSTHESETHREECLASSESOFDEVICESCOMMUNICATEAMONGTHEMSELVESOVERASHAREDSETOFDIGITALSIGNALLINESCALLEDABUSTHEBUSISLOGICALLYORGANIZEDINTOSETSOFADDRESS,DATA,ANDCONTROLLINESTHEADDRESSLINESAREFORCOMMUNICATINGDEVICEADDRESSESWHICHUNIQUELYIDENTIFYAPARTICULARDEVICEONTHEBUSTHEDATALINESAREFORCOMMUNICATINGBINARYDATABETWEENTWOBUSDEVICES,ABUSMASTER,WHICHINITIATESADATATRANSFERBYPLACINGANADDRESSONTHEADDRESSLINES,ANDABUSSLAVE,WHICHREADSANDDECODESTHEADDRESSGENERATEDBYTHEBUSMASTERASITSOWNTHECONTROLLINESAREFORCOORDINATINGACCESSTOTHEBUSANDSELECTINGAMODEOFOPERATIONONTHEBUSSUCHASWRITEDATAORREADDATAMODESFOREXAMPLE,IFTHEBUSMASTERISAMICROPROCESSORANDTHEBUSSLAVEISAMEMORY,THEMICROPROCESSORMAYDIRECTTHEMEMORYTOBEREADBYPLACINGTHEPROPERLOGICLEVELONAWRITE/READCONTROLLINEINTHISWAY,THEMICROPROCESSORGAINSACCESSTOTHEDATASTOREDINTHEMEMORYLOCATIONSPECIFIEDBYTHELOGICLEVELSPLACEDONTHEADDRESSLINESBYTHEMICROPROCESSORABUSCYCLEBEGINSWHENTHEBUSMASTERDIRECTSAWRITEORAREADONTHEBUSTHEBUSCYCLEISCOMPLETEDAFTERALLDATAHASBEENTRANSFERREDACROSSTHEBUSANDTHEBUSMASTERRELEASESCONTROLOFTHEBUSIFTHETWODEVICESCOMMUNICATINGWITHEACHOTHEROVERTHEBUSOPERATEATTHESAMESPEED,THENABUSCYCLEMAYBEACHIEVEDOVERAMINIMUMNUMBEROFCLOCKCYCLESIF,ONTHEOTHERHAND,ABUSDEVICECANONLYTRANSMITORRECEIVEDATAOVERMANYCLOCKCYCLES,THENADELAYMUSTBEINJECTEDINTOTHESTATESEQUENCINGOFTHEFASTERDEVICEINSUCHCASES,A“READY“CONTROLLINEISTYPICALLYACTIVATEDBYTHESLOWERDEVICETOINDICATETOTHEFASTERDEVICETHATDATAISAVAILABLEONTHEBUSORHASBEENTAKENFROMTHEBUSBUSESMAYBEGENERALLYCLASSIFIEDASSYNCHRONOUSORASYNCHRONOUS,WHERESYNCHRONOUSBUSESAREDISTINGUISHEDBYTHEREQUIREMENTTHATALLBUSDEVICESSYNCHRONIZETHEIRUSEOFTHEBUSBYASINGLECLOCKSOURCEORAFUNDAMENTALFREQUENCYANEXAMPLEOFASYNCHRONOUSBUSUSEDINAMICROCOMPUTERISTHEIBMPCATI/OCHANNEL,ATBUSORINDUSTRYSTANDARDARCHITECTUREBUS“ISABUS“PRESENTBUSFREQUENCYSTANDARDSFORTHEISABUSARE8MHZAND10MHZTHEISABUS,ANEXAMPLEOFASYNCHRONOUSBUS,ISUSEDWITHTHEINTEL80386MICROPROCESSORTHEISABUSPROVIDESA16BITDATABUSANDA24BITADDRESSBUSFORPURPOSESOFTHISDISCUSSION,THECONTROLLINESOFTHEISABUSINCLUDEFOURBUSCYCLEDEFINITIONLINESTHEBUSCYCLEDEFINITIONLINESDEFINETHETYPEOFBUSCYCLEBEINGPERFORMEDINTHEFOLLOWINGDEFINITIONS,ANDTHROUGHOUTTHEREMAINDEROFTHISPATENTDOCUMENT,ALLSIGNALNAMESTHATARETERMINATEDWITHANASTERISKINDICATEANACTIVELOWSIGNALABUSCYCLEDEFINITIONLINECALLEDMEMORYREAD“MEMR“ISACTIVEWHENDATAISTOBEREADFROMMEMORYABUSCYCLEDEFINITIONLINECALLEDMEMORYWRITE“MEMW“ISACTIVEWHENDATAISTOBEWRITTENTOMEMORYABUSCYCLEDEFINITIONLINECALLEDI/OREAD“IOR“ISACTIVEWHENDATAISTOBEREADFROMAPERIPHERALDEVICEABUSCYCLEDEFINITIONLINECALLEDI/OWRITE“IOW“ISACTIVEWHENDATAISTOBEWRITTENTOAPERIPHERALDEVICEINADDITIONTOTHEABOVEMENTIONEDBUSCYCLEDEFINITIONSIGNALSTHEREARESOMEMICROPROCESSORSPECIFICSIGNALSTHATAREUSEDINMOSTMICROCOMPUTERSFORSPECIFICALLYINTERFACINGTHEINTEL8086MICROPROCESSORFAMILYTHEREARETWOBUSCONTROLSIGNALSANDTWOBUSARBITRATIONSIGNALSOFPARTICULARIMPORTANCEFORBUSINTERFACINGTHEBUSCONTROLSIGNALSALLOWTHEMICROPROCESSORTOINDICATEWHENABUSCYCLEHASBEGUN,ANDALLOWSOTHERBUSDEVICESTOINDICATEABUSCYCLETERMINATIONTHEADDRESSSTATUS“ADS“SIGNALINDICATESTHATAVALIDBUSCYCLEDEFINITION,ANDADDRESS,ISBEINGDRIVENATTHEOUTPUTPINSOFTHE80386MICROPROCESSORTHETRANSFERACKNOWLEDGE“READY“SIGNALINDICATESTHATTHECURRENTBUSCYCLEISCOMPLETEONESKILLEDINTHETECHNOLOGYWILLUNDERSTANDTHEOPERATIONOFTHEISABUS,OTHERAPPLICABLEINDUSTRYSTANDARDBUSES,ANDTHEINTEL8086MICROPROCESSORFAMILYATLEASTTWOREFERENCESAREAVAILABLEONTHESUBJECTINCLUDINGTHEIBMPCFROMTHEINSIDEOUT,REVISEDEDITION,BYMURRAYSARGENTIIIANDRICHARDLSHOEMAKERANDIBMPCATTECHNICALREFERENCEPUBLISHEDBYIBMCORPORATIONSYNCHRONOUSBUSESAREORDINARILYPREFERREDFORMICROCOMPUTERSSINCETHEYCANOFTENTRANSFERDATAFASTERTHANASYNCHRONOUSBUSESCERTAINAPPLICATIONS,HOWEVER,ESPECIALLYWHERELENGTHYCOMMUNICATIONDISTANCESAREINVOLVED,REQUIREASYNCHRONOUSOR“HANDSHAKEONLY“TYPEBUSESWHENDEVICESARESEPARATEDBYSOMEDISTANCE,THESAMEPHASETRANSITIONOFACOMMONCLOCKCANNOTBEGUARANTEEDTHEPRIMARYDISADVANTAGEOFTHESYNCHRONOUSISABUSHASONLYRECENTLYBEENRECOGNIZEDBASICALLY,MICROCOMPUTERSAREEVOLVINGDOWNTWOSEPARATEPATHSOFVARIABLESONESETOFVARIABLESISASSOCIATEDWITHTHEBUSDESIGNANDTHEOTHERSETISASSOCIATEDWITHTHEMICROPROCESSORANDMEMORYDESIGNSASYNCHRONOUSBUS,SUCHASTHEISABUS,SHOULDREMAINCONSTANTSOTHATMICROCOMPUTERSINASINGLEPRODUCTLINEAREALLCOMPATIBLETHATIS,APERIPHERALSUCHASAMODEM,PRINTERANDSOONWILLOPERATETHROUGHARESPECTIVECONTROLLERATTHECLOCKFREQUENCYDEFINEDINTHEBUSSPECIFICATIONTHEREFORE,THEBUSSHOULDONLYCHANGETHROUGHMOREEFFICIENTIE,COSTEFFECTIVEDESIGNSWHICHMEETTHESAMESPECIFICATIONSFOREXAMPLE,THEOPERATINGFREQUENCYOFTHEBUSSHOULDREMAINCONSTANTTOASSUREPROPEROPERATIONOFALLPERIPHERALSCONSTRUCTEDINACCORDANCEWITHTHEBUSSTANDARDINCONTRAST,MICROPROCESSORANDMEMORYTECHNOLOGIESARERAPIDLYEVOLVINGINFUNCTIONALITYANDPERFORMANCEFOREXAMPLE,THEMICROPROCESSORCHANGESINARCHITECTURALDEFINITIONEG,NUMBEROFPINS,INSTRUCTIONSETS,ETCANDCLOCKFREQUENCYEG,16MHZ,25MHZ,33MHZ,THECACHEBECOMESMORESOPHISTICATED,COPROCESSORSBECOMEAPARTOFTHEMICROCOMPUTERARCHITECTUREEG,INTEL80387NUMERICCOPROCESSOR,ANDMAINMEMORYBECOMESFASTERASANEXAMPLEOFMEMORYEVOLUTION,CONSIDERDYNAMICRANDOMACCESSMEMORY,OR“DRAM“ASDRAMTECHNOLOGYIMPROVES,THEOPPORTUNITYFORIMPROVEDSYSTEMPERFORMANCEBECOMESCLEARINTHEEARLYDAYSOFPERSONALCOMPUTERS,THECOMMONDRAMCHIPBEINGUSEDINMICROCOMPUTERSWAS64K165,5361BITS,HAVINGANACCESSTIMEOF150NANOSECONDSRECENTLY,ASTANDARDIE,READILYAVAILABLEANDCOSTEFFECTIVEDRAMSIZEUSEDBYMICROCOMPUTERMANUFACTURERSWAS256K1,HAVINGANACCESSTIMEOF100NANOSECONDSPRESENTLY,ADRAMCHIPSTANDARDOF1M1IE,1,048,5761BITS,HAVINGANACCESSTIMEOF80NANOSECONDSORLESSISEVOLVINGASACOMMERCIALLYFEASIBLESTANDARD,ANDTHETECHNOLOGYTRENDISTOWARDA16MBY1BITCHIPITISDESIREABLETOISOLATETHEMEMORYANDMICROPROCESSORFROMTHESYNCHRONOUSI/OBUSDESIGNSOTHATDIFFERENTDRAMANDMICROPROCESSORSATDIFFERENTOPERATINGFREQUENCIESCANBEUSEDWITHOUTAFFECTINGTHESYNCHRONOUSI/OBUSDESIGNOTHERWISE,IFTHESYNCHRONOUSBUSISNOTISOLATEDFROMTHECOMPUTATIONANDSTORAGEELEMENTS,EACHTECHNOLOGICALIMPROVEMENTINMEMORYORMICROPROCESSORPRODUCTSWILLREQUIREUNIQUEINTERFACECIRCUITRYTOSCALEDOWNCOMMUNICATIONSPEEDWITHOTHERDEVICESACROSSTHESYNCHRONOUSBUSCONSEQUENTLY,ANEEDEXISTSFORIMPROVEMENTSINMICROCOMPUTERSYSTEMSTOISOLATEI/OCHANNELDESIGNFROMMEMORYANDMICROPROCESSORDESIGNS中文譯文單片機(jī)工作原理在通過端口把單片機(jī)連接到個(gè)人電腦上的操作中連接電纜也包含在這個(gè)系統(tǒng)中。單片機(jī)安裝有一個(gè)8751芯片,這個(gè)芯片內(nèi)部的ROM包含多種功能實(shí)時(shí)監(jiān)控器通過PC的串行端口進(jìn)行聯(lián)系。監(jiān)控器包含一個(gè)行匯編，反匯編，斷點(diǎn)，單步和檢驗(yàn)及存儲器、寄存器間內(nèi)容進(jìn)行交換的設(shè)備。監(jiān)控器的一個(gè)特殊功能是存儲單片機(jī)開發(fā)板RAM中的程序。該方法的優(yōu)點(diǎn)是直接進(jìn)入到由8051保存的I/O端口，因此，一個(gè)昂貴的電路仿真（ICE）包是不必需的。一旦單片機(jī)開發(fā)系統(tǒng)方案已經(jīng)完成便可以輕松地通過一個(gè)EPROM將程序轉(zhuǎn)移到另一個(gè)8751ROM。第二個(gè)8751芯片現(xiàn)在包含控制程序，可以從程序編程器中移除并且安裝到單片機(jī)。最重要的，因?yàn)橹苯釉L問輸入/輸出端口的8751一直保留在開發(fā)階段，因此外圍I/O和地址解碼芯片是不需要的，只有8751芯片是必需的。因此，單片機(jī)控制，不是多芯片控制得以實(shí)現(xiàn)。單片機(jī)集成板的特點(diǎn)為微控制器芯片與單片機(jī)的終端設(shè)備都為40WAYDIL插座。板子的開發(fā)為電纜連接更加簡單方便。8751ICS應(yīng)該是單獨(dú)購買。除了單片機(jī)開發(fā)系統(tǒng)和目標(biāo)板，一系列附加板子是單獨(dú)提供的這些包括端口顯示器，多通道ADC，螺絲終端板和輸出驅(qū)動板。將語音輸入到一臺計(jì)算機(jī)是人機(jī)通信最原始的形式。過去幾年來的研究成果表明，通過聲音進(jìn)行人機(jī)通信的技術(shù)成為了一項(xiàng)全新的通信服務(wù)技術(shù)，這項(xiàng)服務(wù)可以提高人的能力，為社會服務(wù)，并提高生產(chǎn)力。語音識別可以被定義為一種把聲音數(shù)據(jù)作為輸入并能辨別單詞和語法的技術(shù)。語音識別系統(tǒng)有兩方面的優(yōu)點(diǎn)（1）它是一種非常簡單的技術(shù)手段，非專業(yè)的計(jì)算機(jī)人員也可以把數(shù)據(jù)輸入電腦。（2）在某些應(yīng)用方面，如半自動質(zhì)量控制檢查程序，計(jì)算機(jī)用戶需要去做其它方面的任務(wù)。語音識別是更廣泛的語音處理技術(shù)的一部分，它涉及電腦技術(shù)鑒定或?qū)φZ音輸入的核實(shí)，電腦語音合成，對已存儲語音的反應(yīng)，計(jì)算機(jī)的物理分析和對聲音輸入者心理狀態(tài)的分析，高效率傳輸口語對話，語音檢測，采取機(jī)器語言，并聽取人類的口令依靠的是綜合語音應(yīng)用系統(tǒng)和語音識別。體現(xiàn)語音信號的許多不同特征已經(jīng)被提出。這些包括能源和零交叉率，共振峰濾波，短時(shí)譜，波形數(shù)字化和線性預(yù)測編碼（LPC）等。選擇一個(gè)功能較另一組的動機(jī)往往是很復(fù)雜的，它受限于系統(tǒng)。如成本，速度，反應(yīng)時(shí)間，電腦的復(fù)雜程度等所有可以考慮的特征。有很多分類的計(jì)算機(jī)，從家庭和辦公室使用的廉價(jià)的微型計(jì)算機(jī)，到在大學(xué)和研究實(shí)驗(yàn)室使用的液體冷卻的超級計(jì)算機(jī)。本發(fā)明涉及微型計(jì)算機(jī)，也稱為“個(gè)人電腦”。微機(jī)可被定義為一個(gè)“由一個(gè)大規(guī)模的集成電路組成的微處理器”，例如英特爾8086的產(chǎn)品家族，目前包括8086，80286，80386和80486微處理器。雖然微處理器是微機(jī)的核心和主要特征，但它不是很有用，除非它和內(nèi)存還有輸入輸出端口集成在一起，這三類設(shè)備間進(jìn)行通信是在一個(gè)共享的數(shù)字信號線上稱為總線?？偩€在邏輯上是由一系列的地址，數(shù)據(jù)和控制線構(gòu)成。地址線是在總線上唯一被確定的通信設(shè)備的地址。數(shù)據(jù)線是在兩個(gè)總線設(shè)備間傳送二進(jìn)制數(shù)據(jù)，總線主機(jī)是通過放置地址總線的一個(gè)地址進(jìn)行數(shù)據(jù)轉(zhuǎn)換，總線附屬是讀取和解碼。把總線主機(jī)產(chǎn)生的地址作為自己的地址。控制總線是協(xié)調(diào)總線入口和選擇一個(gè)操作總線的合適模式，例如數(shù)據(jù)輸入模式和數(shù)據(jù)讀出模式。例如，如果總線主機(jī)是微處理器，總線附屬是一個(gè)內(nèi)存，微處理器的內(nèi)存可直接被讀出通過在讀寫控制線上找尋合適的邏輯電平。這樣，微處理器能夠訪問由微處理器的地址線的邏輯電平確定的存儲單元中存儲的數(shù)據(jù)。當(dāng)總線主機(jī)開始在總線上的讀寫時(shí)一個(gè)總線周期便開始了。當(dāng)所有數(shù)據(jù)在總線上翻譯后總線周期釋放了對總線的控制一個(gè)總線周期便完成了，如果兩個(gè)設(shè)備通過總線操作以相同的速度進(jìn)行通信，那么總線周期可能會用最小的周期。如果，另一方面，總線設(shè)備只能發(fā)送或接收數(shù)據(jù)的時(shí)鐘周期，那么速度相對較快的設(shè)備必須進(jìn)行延遲。在這種情況下，已經(jīng)就緒的控制線通常是由慢的裝置啟動然后指示相對較快的設(shè)備總線可以使用或已經(jīng)從總線接受了數(shù)據(jù)。總線一般可劃分為同步或異步，同步總線是由同一時(shí)鐘源下所有總線設(shè)備同時(shí)使用總線來區(qū)別的（或基本頻率）。微機(jī)中一個(gè)同步總線的例子是IBM個(gè)人電腦的I/O通道。目前總線的ISA總線頻率標(biāo)準(zhǔn)是8兆赫和10兆赫。ISA總線，同步總線一個(gè)的例子，用作INTEL80386的微處理器。在ISA總線提供了一個(gè)16位數(shù)據(jù)總線和24位地址總線。對于本次討論目的，ISA總線的控制線，包括4個(gè)總線周期的