GMII接口分析.doc

本文主要分析MII/RMII/SMII，以及GMII/RGMII/SGMII接口的信號(hào)定義，及相關(guān)知識(shí)，同時(shí)本文也對(duì)RJ-45接口進(jìn)行了總結(jié)，分析了在10/100模式下和1000M模式下的連接方法。4. GMII接口分析GMII接口提供了8位數(shù)據(jù)通道，125MHz的時(shí)鐘速率，從而1000Mbps的數(shù)據(jù)傳輸速率。下圖定義了RS層的輸入輸出信號(hào)以及STA的信號(hào)： 圖18Reconciliation Sublayer (RS) and STA connections to GMII下面將詳細(xì)介紹GMII接口的信號(hào)定義，時(shí)序特性等。由于GMII接口有MAC和PHY模式，因此，將會(huì)根據(jù)這兩種不同的模式進(jìn)行分析，同時(shí)還會(huì)對(duì)RGMII/TBI/RTBI接口進(jìn)行介紹。4.1 GMII接口信號(hào)定義GMII接口可分為MAC模式和PHY模式，一般說(shuō)來(lái)MAC和PHY對(duì)接，但是MAC和MAC也是可以對(duì)接的。在GMII接口中，它是用8根數(shù)據(jù)線來(lái)傳送數(shù)據(jù)的，這樣在傳送1000M數(shù)據(jù)時(shí)，時(shí)鐘就會(huì)125MHz。GMII接口主要包括四個(gè)部分。一是從MAC層到物理層的發(fā)送數(shù)據(jù)接口，二是從物理層到MAC層的接收數(shù)據(jù)接口，三是從物理層到MAC層的狀態(tài)指示信號(hào)，四是MAC層和物理層之間傳送控制和狀態(tài)信息的MDIO接口。GMII接口的MAC模式定義： 注意在表7中，信號(hào)GTX_CLK對(duì)于MAC來(lái)說(shuō)，此時(shí)是Output信號(hào)，這一點(diǎn)和MII接口中的TX_CLK的Input特性不一致。GMII接口PHY模式定義：表8注意在表8中，信號(hào)GTX_CLK對(duì)于PHY來(lái)說(shuō)，此時(shí)是Input信號(hào)，這一點(diǎn)和MII接口中的TX_CLK的Output特性不一致。4.2 GMII接口時(shí)序特性在GMII接口中，TX通道參考時(shí)鐘是GTX_CLK，RX通道參考時(shí)鐘是RX_CLK，802.3-2005定義了它們之間的關(guān)系。圖19 GMII signal timing at receiver input 由圖19可知，Spec只定義了TX通道和RX通道中接收端Setup時(shí)間和Hold時(shí)間。很明顯，即該Spec只對(duì)TX通道上PHY這一側(cè)的接收特性作了定義，而對(duì)TX通道MAC那一側(cè)的發(fā)送特性并沒(méi)有定義。IC Vendor可在TX通道那一側(cè)的MAC的發(fā)送特性作適當(dāng)調(diào)整，只要最終的時(shí)序滿足TX通道上PHY這一側(cè)的接收特性就可以。同樣的道理，該Spec只對(duì)RX通道上MAC這一側(cè)的接收特性作了定義，而對(duì)RX通道PHY那一側(cè)的發(fā)送特性并沒(méi)有定義。IC Vendor可在RX通道那一側(cè)的PHY的發(fā)送特性作適當(dāng)調(diào)整，只要最終的時(shí)序滿足RX通道上MAC這一側(cè)的接收特性就可以。圖20 Setup和Hold Time的值從圖20可以看出，這里有兩組setup和hold時(shí)間。其中第一組Spec則是根據(jù)圖21給定的測(cè)試電路定義的，即該Spec未考慮PCB上傳輸線的不匹配等影響。而第二組Spec則是定義了receiver at its input pins的時(shí)間要求，它考慮了PCB上傳輸線的長(zhǎng)度不匹配等影響。一般IC Vendor需要按照第二組Spec來(lái)設(shè)計(jì)它們的IC。(Two sets of setup and hold time parameters are specified in Fig. 20. The first set, tSETUP and tHOLD, applies to the source of a synchronous GMII signal and its clock and is measured using the “GMII Setup and Hold Time Test Circuit,” which has transmission lines with matched propagation delays in the “clock” and“signal” paths. The second set, tSETUP(RCVR) and tHOLD(RCVR), applies to the GMII receiver and specifies the minimum setup and hold times available to the GMII receiver at its input pins. The difference between the two sets of setup and hold time parameters provides margin for a small amount of mismatch in the propagation delays of the “clock” path and the “signal” paths in GMII applications)。圖21 GMII接口Setup和Hold Time測(cè)試電路 4.3 GMII信號(hào)功能特性： GTX_CLK (transmit clock)，GTX_CLK (Transmit Clock)是一個(gè)連續(xù)的時(shí)鐘信號(hào)（即系統(tǒng)啟動(dòng)，該信號(hào)就一直存在），它是TX_EN, TXD, and TX_ER(信號(hào)方向?yàn)閺腞S到PHY)的參考時(shí)鐘，PHY端在信號(hào)的上升沿采樣，GTX_CLK由MAC驅(qū)動(dòng)。GTX_CLK的時(shí)鐘頻率是數(shù)據(jù)傳輸速率的12.5，即125MHz。：對(duì)于同樣的RX_CLK，它與TX_CLK具有相同的要求，所不同的是它是RX_DV, RXD, and RX_ER(信號(hào)方向是從PHY到RS)的參考時(shí)鐘，MAC端在時(shí)鐘的上升沿采樣。RX_CLK是由PHY驅(qū)動(dòng)，PHY可能從接收到的數(shù)據(jù)中提取時(shí)鐘RX_CLK，也有可能從一個(gè)名義上的參考時(shí)鐘(e.g., the TX_CLK reference)來(lái)驅(qū)動(dòng)RX_CLK：GMII接口的發(fā)送時(shí)序如圖22所示，接收時(shí)序如圖23所示，至于其它信號(hào)的功能特性以及在數(shù)據(jù)傳輸過(guò)程中，不同信號(hào)的邏輯變化所代表的意義，這里不再描述，大體上和“MII信號(hào)功能特性”一節(jié)中描述類(lèi)似，讀者可以參閱802.3-3005的Spec。圖22 GMII信號(hào)發(fā)送時(shí)序圖23 GMII信號(hào)接收時(shí)序4.4 GMII的管理MDIO接口：關(guān)于GMII的管理MDIO接口，這里也不再描述，它在硬件設(shè)計(jì)上同MII的管理MDIO接口一節(jié)的描述。4.5 Electrical Character GMII接口的電氣特性可以分為DC characteristics和AC characteristics。 針對(duì)于DC電氣特性而言，All GMII drivers and receivers shall comply with the dc parametric attributes specified in Table 357. The potential applied to the input of a GMII receiver may exceed the potential of the receivers power supply (i.e., a GMII driver powered from a 3.6 V supply driving VOHinto a GMII receiver powered from a 2.5 V supply). Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications.針對(duì)于AC電氣特性而言，The GMII ac electrical characteristics are specified in a manner that allows the implementor flexibility in selecting the GMII topologies its devices support and the techniques used to achieve the specified characteristics. All GMII devices are required to support point-to-point links. The electrical length of the circuit board traces used to implement these links can be long enough to exhibit transmission line effects and require some form of termination. The implementor is allowed the flexibility to select the driver output characteristics and the termination technique and components to be used with its drivers for point-to-point links. Implementors may elect to support other GMII topologies in addition to the point-to-point topology and may specify different termination techniques and components for each supported topology.Since the output characteristics and output voltage waveforms of GMII drivers depend on the termination technique and the location of the termination components, the ac output characteristics of GMII drivers are not explicitly specified. Rather, the ac characteristics of the signal delivered to a GMII receiver are specified. These characteristics are independent of the topology and termination technique and apply uniformly to all GMII applications. 5. RGMII接口分析5.1 RGMII接口信號(hào)定義：RGMII接口（Reduced GMII接口）是簡(jiǎn)化的GMII接口。它也分為MAC模式和PHY模式。RGMII接口的MAC模式定義：表9RGMII接口的PHY模式定義： 表10由表9表10可知，RGMII接口相對(duì)于GMII接口，在TXD和RXD上總共減少了8根數(shù)據(jù)線。 5.2 RGMII接口時(shí)序特性：圖24 RGMII接口TX通道MAC側(cè)發(fā)送特性雖然RGMII接口中，信號(hào)線減半，同時(shí)GTX_CLK和RX_CLK還是125MHz，為了達(dá)到1000Mbit的