半導(dǎo)體器件物理課件4.pdf

Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 第一章第一章 引言引言 第二章第二章 半導(dǎo)體器件物理基礎(chǔ)半導(dǎo)體器件物理基礎(chǔ) 第三章第三章 MOS FETMOS FET基本結(jié)構(gòu)和原理基本結(jié)構(gòu)和原理 第四章第四章 短溝道短溝道MOSMOS器件器件 第五章第五章 存儲(chǔ)器件基礎(chǔ) 不揮發(fā)存儲(chǔ)器件基礎(chǔ) 不揮發(fā) 揮發(fā) 揮發(fā) 第六章第六章 異質(zhì)結(jié)的基本特性和應(yīng)用異質(zhì)結(jié)的基本特性和應(yīng)用 第七章第七章 SOISOI結(jié)構(gòu)和結(jié)構(gòu)和SOI CMOSSOI CMOS器件器件 第八章第八章 納米尺度器件及芯片加工技術(shù)納米尺度器件及芯片加工技術(shù) 章節(jié) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 短溝道MOSFET器件 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 短溝道MOSFET器件物理 1950 1960 1970 1980 1990 2000 2010 2020 2030 1E 3 0 01 0 1 1 10 Shrinking of MOSFETs forecast shrink of 13 year 2 3 years 2 in area shrink 3 years Min feature 祄 Year wS wD wC VD VG Source depletion Drain depletion Charge sharing DIBL Moore s law Short channel ox B BFBT C Q VVV 2 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 1 MOSFET的短溝道效應(yīng)和窄溝道效應(yīng)的短溝道效應(yīng)和窄溝道效應(yīng) 2 小尺寸小尺寸MOSFET的直流特性的直流特性 3 MOSFET的按比例縮小規(guī)律的按比例縮小規(guī)律 章節(jié) 4 實(shí)現(xiàn)短溝道實(shí)現(xiàn)短溝道MOSFET器件的新技術(shù)器件的新技術(shù) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 6 1 一一 MOSFET 的短溝道效應(yīng) 的短溝道效應(yīng) SCE 1 閾值電壓 卷曲 閾值電壓 卷曲 VT roll off 2 漏感應(yīng)勢(shì)壘降低 漏感應(yīng)勢(shì)壘降低 DIBL 3 速度飽和效應(yīng)速度飽和效應(yīng) 4 亞閾特性退化亞閾特性退化 5 熱載流子效應(yīng)熱載流子效應(yīng) MOSFET的短溝道效應(yīng)和窄溝道效應(yīng) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 閾值電壓 卷曲 閾值電壓 卷曲 VT roll off 1 現(xiàn)象現(xiàn)象 短溝道效應(yīng)短溝道效應(yīng) 窄溝道效應(yīng)窄溝道效應(yīng) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 2 短溝道短溝道Vt roll off的原因的原因 長(zhǎng)溝道長(zhǎng)溝道 MOSFET 短溝道短溝道 MOSFET s yx x yx 2 2 s yx y yx x yx 2 2 2 2 GCA 0 2 2 y yx p Si p Si 0 2 2 y yx 多個(gè)耗盡區(qū)對(duì)溝道電荷有影響 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 3 電荷分享模型電荷分享模型 Poon Yau ox B BFBT C Q VVV 2 NMOS ox B BFBT C Q VVV 2 考慮到源 漏 襯底 的耗盡區(qū)對(duì)溝道的電 荷貢獻(xiàn) wS wD wC VD VG Source depletion Drain depletion 溝道長(zhǎng)度繼續(xù)減小溝道長(zhǎng)度繼續(xù)減小 由于源 漏 襯底的 耗盡區(qū)向溝道內(nèi)擴(kuò)展 柵極電壓導(dǎo)致溝道所需 的電荷減少 Vt 降低 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 L L Ld Ld Q Q B B 1 22 1 max max j xdrL 2 1 2 max 2 2 1 2 1122 2 1 max j j BSBBFBT x d L x VVVVV L VT tox VT NA dmax F VT xj VT 因此因此 QB QB 電荷分享因子 電荷分享因子 F 的計(jì)算 的計(jì)算 VDS 0V Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 當(dāng)當(dāng) VDS 0 時(shí)時(shí) VDS F VT 抑制抑制 VT roll off 的措施 的措施 1o xj 2o NA 3o tox 4o VBS 5o VDS Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 反常短溝道效應(yīng) 反常短溝道效應(yīng) RSCE VT roll up 1 現(xiàn)象現(xiàn)象 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 2 原因原因 MOS 重新氧化 重新氧化 RE OX 工藝 工藝 OED 氧化增強(qiáng)擴(kuò)散 氧化增強(qiáng)擴(kuò)散 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 3 分析分析 00 exp GyQyQ fsfs 單位 單位 C cm2 橫向分布的特征長(zhǎng)度橫向分布的特征長(zhǎng)度 源 漏 端雜質(zhì)電荷面密度源 漏 端雜質(zhì)電荷面密度 單位 單位 C 0 00 2exp1 2 GL LC GQ ox fs LWC Q V ox FS T 000 2 0 2exp12 2GLWGQdyyQWQ fs L fsFS Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 窄溝道效應(yīng) 窄溝道效應(yīng) NWE 1 現(xiàn)象現(xiàn)象 W VT 短溝道效應(yīng)短溝道效應(yīng) 窄溝道效應(yīng)窄溝道效應(yīng) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 2 邊緣耗盡效應(yīng)邊緣耗盡效應(yīng) BSBBFBT VVVVV 22 寬溝 ox B C Q ox W BSBBFBT C Q VVVVV 22 窄溝 W d dW d Q Q B Wmax max 2 max 2 2 1 W QB Q W SiO2 dmax x z y 圓弧 圓弧 一般地 引入經(jīng)驗(yàn)參數(shù)一般地 引入經(jīng)驗(yàn)參數(shù) GW W d G Q Q W B Wmax Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 3 三種氧化物隔離結(jié)構(gòu)的三種氧化物隔離結(jié)構(gòu)的 NWE Raised field oxide isolation W VT LOCOS W VT STI W VT 反窄溝道效應(yīng)反窄溝道效應(yīng) inverse NWE Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 4 雜質(zhì)橫向擴(kuò)散的影響雜質(zhì)橫向擴(kuò)散的影響 雜質(zhì)濃度邊緣高 中間低雜質(zhì)濃度邊緣高 中間低 邊緣不易開(kāi)邊緣不易開(kāi) 啟啟 隨著隨著 W VT 窄溝道效應(yīng)窄溝道效應(yīng) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 1 MOSFET的短溝道效應(yīng)和窄溝道效應(yīng)的短溝道效應(yīng)和窄溝道效應(yīng) 2 小尺寸小尺寸MOSFET的直流特性的直流特性 3 MOSFET的按比例縮小規(guī)律的按比例縮小規(guī)律 章節(jié) 4 實(shí)現(xiàn)短溝道實(shí)現(xiàn)短溝道MOSFET器件的新技術(shù)器件的新技術(shù) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 漏感應(yīng)勢(shì)壘降低 漏感應(yīng)勢(shì)壘降低 DIBL 1 現(xiàn)象現(xiàn)象 L 很小時(shí) 很小時(shí) VDS VT DSTDST VVVV 0 DIBL 因子因子 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 2 原因原因 1 電荷分享電荷分享 1 2 1 2 2 1 j D j x y L x 1 2 1 2 1 2 1 j S j B B x y L x Q Q F 2 1 1 DS yy L BSbi A s S VV qN y 2 BSDSbi A s D VVV qN y 2 VDS F VT ox BSBAsDS T LC VVNqyy V 5 0 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 2 電勢(shì)的二維分布電勢(shì)的二維分布 導(dǎo)帶邊導(dǎo)帶邊 Ec Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 短溝道短溝道 MOSFET 的亞閾特性的亞閾特性 1 現(xiàn)象現(xiàn)象 長(zhǎng)溝道長(zhǎng)溝道 短溝道短溝道 IDSst 1 L IDSst 1 L IDSst 與與 VDS 無(wú)關(guān)無(wú)關(guān) VDS IDSst S 與與 L 無(wú)關(guān)無(wú)關(guān) L S 長(zhǎng)溝道長(zhǎng)溝道 MOSFET 短溝道短溝道 MOSFET DIBL Vth 1 0 1 V Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 短溝道短溝道 MOSFET 的亞閾擺幅的亞閾擺幅 隨溝道長(zhǎng)度減小 亞閾值擺幅 subthreshold swing 有增大的趨勢(shì) subthreshold swing 增大 驅(qū)動(dòng)電流 漏電流比減小 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 2 原因原因 PTDSstDSst III 擴(kuò)散短溝 1 亞表面穿通 亞表面穿通 sub surface punchthrough 均勻摻雜襯底均勻摻雜襯底 VT adjust implant 因溝道變短 亞表面容易源漏穿通 漏電流上升 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 亞表面穿通 亞表面穿通 sub surface punchthrough 3 抑制 sub surface punchthrough 的措施 1 選擇合適的選擇合適的 NB 10 chB NN 2 做做 anti punchthrough implant punchthrough stopper implant punchthrough implant PTI Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 PTI 10ln q kT nS x Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 3 Halo implant Halo implant 擴(kuò)散長(zhǎng)度需要很慢 一般B halo implant 需要加 C implant Halo implant 劑量上升 漏結(jié)漏電流上 升 tunneling impact ionization 可以單邊Halo 或雙邊Halo implant Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 熱載流子效應(yīng)抑制熱載流子效應(yīng)抑制 新型漏結(jié)構(gòu)新型漏結(jié)構(gòu) 1 最大漏電場(chǎng) Eymax 飽和時(shí)飽和時(shí) 3 13 1 max 22 0 joxDSsatDSy xtVVE tox 和和 xj 均以均以 cm 為單位為單位 降低 Eymax 措施 tox xj VDS VDD 新型漏結(jié)構(gòu) Graded pn junction 2 雙擴(kuò)散漏 DDD P 比 As 擴(kuò)散系數(shù)大 DDD 應(yīng)用范圍 L 1 5 m Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 3 輕摻雜漏結(jié)構(gòu) LDD Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 LDD 結(jié)構(gòu)的電場(chǎng)分布結(jié)構(gòu)的電場(chǎng)分布 普通 普通 3 13 1 max 22 0 joxDSsatDSy xtVVE LDD 3 13 1 maxmax 22 0 jox n yDSsatDSy xtLEVVE n joxDSsatDSy LxtVVE 3 13 1 max 22 0 LDD 應(yīng)用范圍 L 1 25 m 優(yōu)點(diǎn) 電場(chǎng)降低 漏電流減小 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 小尺寸小尺寸MOSFET的直流特性的直流特性 1 載流子速度飽和效應(yīng)載流子速度飽和效應(yīng) velocity saturation v 不飽和區(qū)不飽和區(qū) v 飽和區(qū)飽和區(qū) v Ey Ey 107cm s Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 長(zhǎng)溝道 短溝道直流特性對(duì)比 2 2 1 DSDSTGSDS VVVVI 長(zhǎng)溝道長(zhǎng)溝道 短溝道短溝道 線性區(qū)線性區(qū) 2 2 1 DSDSTGSDS VVVVI IDS 飽和條件飽和條件 LWCox n LEV LWC satDS oxeff 1 0 LQn TGSDSsat VVV satn vv TGSsat TGSsat DSsat VVLE VVLE V 飽和區(qū)飽和區(qū) 2 2 2 1 2 1 DSsatTGSDSsat VVVI TGSsat TGS oxsatDSsat VVLE VV WCvI 2 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 短溝道 MOSFET 飽和區(qū)特性 計(jì)算溝道中 P 點(diǎn) 速度達(dá)到 vsat 電場(chǎng)達(dá)到 Esat 的電流 區(qū)區(qū) I 2 2 1 1 DSsatDSsatTGSox sat DSsat eff DS VVVV L W C LE V I DSsatTGSoxsatsatnDS VVVCWvWvPQI 區(qū)區(qū) II DSsat I TGSsat TGSsat DSsat VVLE VVLE V TGSsat TGS oxsatDSsat VVLE VV WCvI 2 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 溝道摻雜隨機(jī)分布 dopant random distribution 短溝道器件 溝道摻雜濃度升高且溝道長(zhǎng)度和寬度減小 溝道摻雜隨機(jī)分布 對(duì)閾值電壓偏差的影響增大 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 柵電場(chǎng)導(dǎo)致的mobility degradation 源漏電場(chǎng)導(dǎo)致載流子速度飽和甚至在更小器件中的過(guò)沖 溝道長(zhǎng)度調(diào)制作用 3 Punch through 1 Hot electrons impact ionization gate injection 2 gate break through 寄生效應(yīng) Source Drain 電阻 擊穿性能影響 Avalanche multiplication Drain break through Parasitic Bipolar Transistor 載流子遷移 High Electric Fields 高電場(chǎng)使短溝道MOS管性能變差 短溝道器件中的高電場(chǎng)的影響總結(jié)短溝道器件中的高電場(chǎng)的影響總結(jié) 由于短溝道器件中的電場(chǎng)上升 導(dǎo)致以下效應(yīng) 由于短溝道器件中的電場(chǎng)上升 導(dǎo)致以下效應(yīng) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 1 MOSFET的短溝道效應(yīng)和窄溝道效應(yīng)的短溝道效應(yīng)和窄溝道效應(yīng) 2 小尺寸小尺寸MOSFET的直流特性的直流特性 3 MOSFET的按比例縮小規(guī)律的按比例縮小規(guī)律 章節(jié) 4 實(shí)現(xiàn)短溝道實(shí)現(xiàn)短溝道MOSFET器件的新技術(shù)器件的新技術(shù) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 MOSFET 的按比例縮小規(guī)律的按比例縮小規(guī)律 Moore s Law Continues Transistors doubling every 18 months towards the billion transistor microprocessor Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Transistor Gate Length Scaling Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 International Technology Roadmap of Semiconductors Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 1 Why miniaturization 速度速度 功耗功耗 集成度集成度 功能功能 價(jià)格價(jià)格 功能功能 2 How miniaturization Scaling according to some rules Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 一一 MOSFET 的的 scaling 規(guī)則規(guī)則 1 恒電場(chǎng)恒電場(chǎng) CE scaling 尺寸縮小到尺寸縮小到 1 電壓縮小到電壓縮小到 1 電場(chǎng)不變 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Constant Electric Field Scaling 電場(chǎng)電場(chǎng) yxE x yx x yx x yx yxE xx 襯底摻雜襯底摻雜 AA NN DSDS II 驅(qū)動(dòng)電流驅(qū)動(dòng)電流 電流密度電流密度 I A AI A I AI 2 RC 延遲時(shí)間延遲時(shí)間 GG CRCR 功耗功耗 22 PIVVIVIP 電路密度 電路密度 CD A ACD 2 2 1 1 耗盡層等比縮小 2 2 1 1 DSsatDSsatTGSox sat DSsat eff DS VVVV L W C LE V I Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Constant Electrical Field Scaling Rule Requirements Device dimensions L L Channel length W W Channel width t ox tox Oxide thickness x j xj S D depth Device doping N A NA Applied voltage V A VA Results device parameters Electrical field E x y E x y Electric potential x y x y Drain depletion width W D WD Gate capacitance C G CG Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Constant Electrical Field Scaling Rule cont Drain current I I Not valid for subthreshold region Current density I A I A Channel resistance R R Results circuit performance Circuit delay time RC Power IV P P 2 Power density P A P A P A Circuit density CD CD 2CD Assumption Threshold voltage V T VT Not valid Build in voltage V bi V DD Not valid Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 2 恒電壓恒電壓 CV scaling 1o 為了應(yīng)用和標(biāo)準(zhǔn)化 為了應(yīng)用和標(biāo)準(zhǔn)化 VDD 不能連續(xù)不能連續(xù) scaling VDD 5 0 V 0 8 m 2o VT 和和 Vbi scaling 困難困難 目的目的 尺寸縮小到尺寸縮小到 1 電壓不變電壓不變 電場(chǎng)增大到電場(chǎng)增大到 倍倍 做法做法 問(wèn)題 高場(chǎng)造成遷移率下降 熱載流子效應(yīng)問(wèn)題 高場(chǎng)造成遷移率下降 熱載流子效應(yīng) Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 3 準(zhǔn)恒電壓準(zhǔn)恒電壓 QCV scaling Generalized scaling 做法 尺寸縮小到做法 尺寸縮小到 1 電場(chǎng)增加到電場(chǎng)增加到 倍 通常倍 通常 1 恒電場(chǎng) 恒電場(chǎng) 1 恒電壓 恒電壓 AA NN yxyx 功耗密度功耗密度 P A 2 23 A P AP AP 3 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Generalized Scaling Rule 1 Requirements Device dimensions L L Channel length W W Channel width t ox tox Oxide thickness x j xj S D depth Device doping N A NA Applied voltage V A VA Results device parameters Electrical field E x y E x y Electric potential x y x y Drain depletion width W D WD Gate capacitance C G CG Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Generalized Scaling Rule 1 cont Drain current I 2 I Not valid for subthreshold region Current density I A 2 I A Channel resistance R R Results circuit performance Circuit delay time RC Power IV P 3 2 P Power density P A P A 3 P A Heavy burden Circuit density CD CD 2CD Assumption Threshold voltage V T VT More valid than in CE Build in voltage V bi V DD Not valid Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 4 亞閾值亞閾值 scaling Subthreshold scaling 強(qiáng)反型 強(qiáng)反型 ON 態(tài) 態(tài) IDS 可以可以 scaling DSDS II CE scaling DSDS II 2 Generalized scaling 弱反型 弱反型 OFF 態(tài) 態(tài) IDSst 不能不能 scaling Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Subthreshold Scaling 用亞閾特性 不變壞 作為準(zhǔn)則來(lái)用亞閾特性 不變壞 作為準(zhǔn)則來(lái) scaling 器件器件 長(zhǎng)溝道長(zhǎng)溝道 MOSFET IDSst 基本上與基本上與 VDS 無(wú)關(guān) 無(wú)關(guān) 短溝道短溝道 MOSFET IDSst 與與 VDS 有關(guān)有關(guān) 經(jīng)驗(yàn)準(zhǔn)則經(jīng)驗(yàn)準(zhǔn)則 當(dāng)當(dāng) VDS 增加增加 0 5 V IDSst 的增加的增加 10 短溝道 短溝道 經(jīng)驗(yàn)公式 經(jīng)驗(yàn)公式 3 1 2 minDSoxj WWtxAL m m 0 4 1 3 m 長(zhǎng)溝道長(zhǎng)溝道 短溝道短溝道 Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 二二 Scaling 的限制及對(duì)策 新結(jié)構(gòu) 的限制及對(duì)策 新結(jié)構(gòu) 1 xj xj RS RD gD 線性線性 gm 飽和飽和 對(duì)策 對(duì)策 自對(duì)準(zhǔn)金屬硅化物技術(shù)自對(duì)準(zhǔn)金屬硅化物技術(shù) Salicide Self aligned silicide 3 1 2 minDSoxj WWtxAL Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 2 tox Fowler Nordheim 隧穿電流 隧穿電流 oxox EBAEJ exp 2 要求 要求 Jg low leakage slowly low power low Vt thin gate oxide high speed high leakage high performance Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 30nm planar bulk MOSFET Agressively scaled planar bulk device optical lithography 248 nm phase shift mask oxide thickness 0 8 nm Source INTEL IEDM 2000 Top view cross section 0 8 nm SiO2 gate dielectric VDD 0 85 V Ioff 100nA m S 100mV dec DIBL 100mV Ion 500 A m gm 1200mS mm gate delay 0 9 psec 30nm planar bulk CMOS is achievable with todays equipment retrograded well no halo all T 柵電容增大 亞閾值擺幅和驅(qū)動(dòng)電流 改善 襯底體積減小 漏電流降低 缺點(diǎn) 制造復(fù)雜 閾值電壓難用離子注入調(diào)節(jié) fully depleted 48nm FinFET DRAM Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Gate all around transistor Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Raised S D MOSFET 50 increase of ID in NMOS 30 increase of ID in PMOS Source drain series resistance can be reduced By epitaxy Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 U shape device 6xnm DRAM with U shape device Channel is recessed into the substrate Ultra low leakage current 1T 1C DRAM Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 SOI MOSFET DST Depleted Substrate Transistor Fully Depleted FD SOI MOSFET Lg 65 nm 75 mV dec 95 mV dec 低漏電流 小寄生電容低漏電流 小寄生電容 SOI襯底昂貴 襯底昂貴 需考慮浮體效應(yīng)需考慮浮體效應(yīng) floating body effect Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Vertical transistor n Drain p epi Drain Gate Gate Gate Gate A Vertical Replacement Gate VRG MOSFET PSG PSG SiO2 Si Chemical Mechanical Polishing Si epitaxy deposition poly Source deposition nitride spacer formation open gate grown gate oxide poly deposition patterning SD extension drive in Dr P F Wang Fudan University Advanced semiconductor devices and physics 2012 10 Planar Layout from 0 25 m ASIC library VRG Layout using similar 0 25 m design rules VRG vs Planar Similar packing density Up to double dri