外文翻譯--SJA1000--獨立的CAN控制器

黑龍江工程學院本科生畢業(yè)設(shè)計 1 附錄 A 英文原文 SJA1000 Stand-alone CAN controller 1. INTRODUCTION The SJA1000 is a stand-alone CAN Controller product with advanced features for use in automotive and general industrial applications. It is intended to replace the PCA82C200 because it is hardware and software compatible. Due to an enhanced set of functions this device is well suited for many applications especially when systemoptimization, diagnosis and maintenance are important. This report is intended to guide the user in designing complete CAN nodes based on the SJA1000. The report provides typical application circuit diagrams and flow charts for programming. 2. OVERVIEW The stand-alone CAN controller SJA1000 1 has two different Modes of Operation: 1.BasicCAN Mode (PCA82C250 compatible). 2.PeliCAN Mode. Upon Power-up the BasicCAN Mode is the default mode of operation. Consequently, existing hardware and software developed for the PCA82C250 can be used without any change. In addition to the functions known from the PCA82C250 , some extra features have been implemented in this mode which make the device more attractive. However, they do not influence the compatibility to the PCA82C250. The PeliCAN Mode is a new mode of operation which is able to handle all frame types according to CAN specification 2.0B. Furthermore it provides a couple of enhanced features which makes the SJA1000 suitable for a wide range of applications. 2.1 SJA1000 Features The features of the SJA1000 can be clustered into three main groups: 1.Well-established PCA82C200 Functions Features of this group have already been implemented in the PCA82C250. 2.Improved PCA82C200 Functions Partly these functions have already been implemented in the PCA82C250. However, in the SJA1000 they have been improved in terms of speed, size or performance. 3.Enhanced Functions in PeliCAN Mode 黑龍江工程學院本科生畢業(yè)設(shè)計 2 In PeliCAN Mode the SJA1000 offers a couple of Error Analysis Functions supporting diagnosis, system maintenance and optimization. Furthermore functions for general CPU support and System Self Test have been added in this mode. 2.2 CAN Node Architecture Generally each CAN module can be divided into different functional blocks. The connection to the CAN bus linesis usually built with a CAN Transceiver optimized for the applications. The transceiver controls thelogic level signals from the CAN controller into the physical levels on the bus and vice versa. The next upper level is a CAN Controller which implements the complete CAN protocol defined in the CAN Specification 8. Often it also covers message buffering and acceptance filtering. All these CAN functions are controlled by a Module Controller which performs the functionality of the application. For example, it controls actuators, reads sensors and handles the man-machine interface (MMI). As shown in Figure 1 the SJA1000 stand-alone CAN controller is always located between a microcontroller and the transceiver, which is an integrated circuit in most cases. Figure 1 CAN Module Set-up 2.3 Block Diagram The following figure shows the block diagram of the SJA1000. The CAN Core Block controls the transmission and reception of CAN frames according to the CAN specification. The Interface Management Logic block performs a link to the external host controller which can be a microcontroller or any other device. Every register access via the SJA1000 黑龍江工程學院本科生畢業(yè)設(shè)計 3 multiplexed address/data bus and controlling of the read/write strobes is handled in this unit. Additionally to the BasicCAN functions known from the PCA82C250, new PeliCAN features have been added. As a consequence of this, additional registers and logic have been implemented mainly in this block. Figure 2: Block Diagram SJA1000 The Transmit Buffer of the SJA1000 is able to store one complete message (Extended or Standard). Whenever a transmission is initiated by the host controller the Interface Management Logic forces the CAN Core Block to read the CAN message from the Transmit Buffer. When receiving a message, the CAN Core Block converts the serial bit stream into parallel data for the Acceptance Filter. With this programmable filter the SJA1000 decides which messages actually are received by the host controller. All received messages accepted by the acceptance filter are stored within a Receive FIFO. Depending on the mode of operation and the data length up to 32 messages can be stored. This enables the user to be more flexible when specifying interrupt services and interrupt priorities for the system because the probability of data overrun conditions is reduced extremely. 3. SYSTEM For connection to the host controller, the SJA1000 provides a multiplexed address/data bus and additional read/write control signals. The SJA1000 could be seen as a peripheral memory mapped I/O device for the host controller. 3.1 SJA1000 Application Configuration Registers and pins of the SJA1000 allow to use all kinds of integrated or discrete CAN transceivers. Due to the flexible microcontroller interface applications with different microcontrollers are possible. 黑龍江工程學院本科生畢業(yè)設(shè)計 4 Figure 3 Typical SJA1000 Application 3.2 Power Supply The SJA1000 has three pairs of voltage supply pins which are used for different digital and analog internal blocks of the CAN controller. 1.VDD1 / VSS1: internal logic (digital). 2.VDD2 / VSS2: input comparator (analog). 3.VDD3 / VSS3: output driver (analog). The supply has been separated for better EME behaviour. For instance the VDD2 can be de-coupled via an RC filter for noise suppression of the comparator. 3.3 Reset For a proper reset of the SJA1000 a stable oscillator clock has to be provided at XTAL1 of the CAN controller,see also chapter 3.4. An external reset on pin 17 is synchronized and internally lengthened to 15 TXTAL. This guarantees a correct reset of all SJA1000 registers (see1). Note that an oscillator start-up time has to be taken into account upon power-up. 3.4 Oscillator and Clocking Strategy The SJA1000 can operate with the on-chip oscillator or with external clock sources. Additionally the CLK OUT pin can be enabled to output the clock frequency for the host controller. Figure 4 shows four different clocking principles for applications with the SJA1000. If the CLK OUT signal is not needed, it can be switched off with the Clock Divider register (Clock Off = 1). This will improve the EME performance of the CAN node. The frequency of the CLK OUT signal can be changed with the Clock Divider Register: CLK OUT = f XTAL / Clock Divider factor (1,2,4,6,8,10,12,14). 黑龍江工程學院本科生畢業(yè)設(shè)計 5 Upon power up or hardware reset the default value for the Clock Divider factor depends on the selected interface mode (pin 11). If a 16 MHz crystal is used in Intel mode, the frequency at CLK OUT is 8 MHz. In Motorola mode a Clock Divider factor of 12 is used upon reset which results in 1,33 MHz in this case. Figure 4 Clocking Schemes 3.4.1 Sleep and Wake-up Upon setting the Go To Sleep bit in the Command Register (BasicCAN mode) or the Sleep Mode bit in the Mode Register (PeliCAN mode) the SJA1000 will enter Sleep Mode if there is no bus activity and no interrupt is pending. The oscillator keeps on running until 15 CAN bit times have been passed. This allows a microcontroller clocked with the CLK OUT frequency to enter its own low power consumption mode. If one of three possible wake-up conditions occurs the oscillator is started again and a Wake-up interrupt is generated. As soon as the oscillator is stable the CLK OUT frequency is active. 3.5 CPU Interface The SJA1000 supports the direct connection to two famous microcontroller families: 80C51 and 68xx. With the MODE pin of the SJA1000 the interface mode is selected. Intel Mode: MODE = high. Motorola Mode: MODE = low. The connection for the address/data bus and the read/write control signals in both Intel and Motorola mode is shown in Figure 5. For Philips 8-bit microcontrollers based on the 80C51 family and the 16-bit microcontrollers with XA architecture the Intel Mode is used. For other controllers additional glue logic is necessary for adaptation of the 黑龍江工程學院本科生畢業(yè)設(shè)計 6 address/data bus and the control signals. However, it has to be made sure that no write pulses are generated during power-up. Another possibility is to disable the CAN controller with a high-level on the chip select input in this time. Figure 5 CPU Interface of the SJA1000 3.6 Physical Layer Interface For compatibility purposes with the PCA82C250, the SJA1000 includes an analog receive input comparator circuit. This integrated comparator can be used if the transceiver function is realized with discrete components. Figure 6 SJA1000 Receive Input Comparator If an external integrated transceiver circuit is used and the comparator bypass function is not enabled in the Clock Divider Register, the RX1 input has to be connected to a reference voltage of 2.5V (reference voltage output of existing transceiver circuits). Figure 6 黑龍江工程學院本科生畢業(yè)設(shè)計 7 shows the equivalent circuits for both configurations: CBP = active and CBP = inactive. Additionally the path for the wake-up signal is drawn. For all new applications where an integrated transceiver circuit is used, it is recommended to activate the comparator bypass function of the SJA1000 (Figure 7). If this function is enabled, a schmitt-trigger input is used and the internal propagation delay TD2 is much shorter as the delay TD1. of the receive comparator. This has a positive impact on the maximum bus length6. Additionally, it will reduce the supply current in sleep mode significantly. Figure 7 Standard application with integrated transceiver circuit 黑龍江工程學院本科生畢業(yè)設(shè)計 8 附錄 B 英文翻譯 SJA1000 獨立的 CAN 控制器 1.介紹 控制器局部網(wǎng) CAN 是一個串行的異步的多主機的通訊協(xié)議 SJA1000 是一個獨立的 CAN 控制器它在汽車和普通的工業(yè)應(yīng)用上有先進的特征由于硬件和軟件的兼容它將會替代 PCA82C250。 它與 PCA82C250 相比具有更先進的特征因此特別適合于轎車內(nèi)的電子模塊傳感器制動器的連接和通用工業(yè)應(yīng)用中特別是系統(tǒng)優(yōu)化系統(tǒng)診 斷和系統(tǒng)維護時特別重要。 本文傾向于在設(shè)計 SJA1000 為基礎(chǔ)的 CAN 節(jié)點上引導用戶同時還提供典型的應(yīng)用電路圖和用于編程的流程圖。 2.概述 獨立的 CAN控制器 SJA1000有 2個不同的操作模式： 1.BasicCAN 模式 (PCA82C250兼容 )。 2.PeliCAN 模式。 上電時 BasicCAN模式是默認的操作模式因此已經(jīng)使用 PCA82C250開發(fā)出的硬件和軟件可以直接被 SJA1000 使用而不用作任何修改 PeliCAN 模式是操作的新模式它能夠處理所有的 CAN2.0B 定義的幀類型而且它還提供一些增強 功能使 SJA1000 能應(yīng)用于更寬的領(lǐng)域。 2.1 SJA1000 特征 SJA1000的特征能分成 3組 ： 1.已建立好的 PCA82C250功能 這組的特征在 PCA82C250里已經(jīng)生效 。 2.提高的 PCA82C200功能 部份這些功能在 PCA82C250 里已經(jīng)生效但是在 SJA1000 里它們在速度大小和性能方面已得到提高 。 3.在 PeliCAN模式里的增強功能 在 PeliCAN 模式里 SJA1000 支持一些錯誤分析功能如支持系統(tǒng)診斷系統(tǒng)維護系統(tǒng)優(yōu)化而且這個模式里也加入了對一般 CPU的支持和系統(tǒng)自身測試的功能。 黑龍江工程學院本科生畢業(yè)設(shè)計 9 2.2 CAN 節(jié)點結(jié)構(gòu) 一般來說每個 CAN模塊能夠被分成不同的功能塊 CAN總線的連接通常由被優(yōu)化的 CAN收發(fā)器建立收發(fā)器控制邏輯電平信號從 CAN控制器到達總線上的物理層反之亦然。 上面一層是一個 CAN 控制器它執(zhí)行在 CAN 規(guī)約里定義的 CAN 協(xié)議它通常用于信息緩沖和驗收濾波。 而所有這些 CAN 功能都被一個模塊控制器控制它用于執(zhí)行功能性的應(yīng)用例如控制調(diào)節(jié)器讀傳感器和處理人機接口 MMI。 如圖 1所示 ， SJA1000獨立的 CAN控制器總是位于微型控制器和收發(fā)器之間在一般情況下這個控制器是一個集成電路。 圖 1 CAN模塊裝置 2.3 方塊圖 下圖是 SJA1000的方塊圖。 圖 2 SJA1000的方塊圖 根據(jù) CAN規(guī)約 CAN核心模塊控制 CAN幀的發(fā)送和接收。 接口管理邏輯完成對外部主控制器的連接該控制器能可以是微型控制器或其他器件經(jīng)過 SJA1000 復用的地址 /數(shù)據(jù)總線訪問寄存器和控制讀 /寫選通信號都在這里處理另外除了 PCA82C200 已有的 BasicCAN 功能還加入了一個新的 PeliCAN 功能因此附加的寄存器和邏輯電路主要在這塊里生效。 黑龍江工程學院本科生畢業(yè)設(shè)計 10 SJA1000 的發(fā)送緩沖器能夠存儲一個完整的信息擴展的或標準的無論什么時候主控制器初始化發(fā)送接口管理邏輯會迫使 CAN核心塊從發(fā)送緩沖器讀 CAN 信息。 當收到一個信息時 CAN 核心塊將串行位流轉(zhuǎn)換成用于驗收濾波器的并行數(shù)據(jù)通過這個可編程的濾波器 SJA1000能確定哪些信息實際上被主控制器收到。 所有收到的信息由驗收濾波器接收并存儲在接收 FIFO 儲存信息的多少由工作模式?jīng)Q定而最多能存儲 32 個信息因為數(shù)據(jù)溢出的可能性被大大降低這使用戶能更靈活地指定中斷服務(wù)和中斷優(yōu)先級。 3.系統(tǒng) 為了連接到主控制器 SJA1000 提供一個復用的地址 /數(shù)據(jù)總線和附加的讀 /寫控制信號 SJA1000能被看作外圍 存儲器并為主控制器映射 I/O設(shè)備。 3.1 SJA1000 應(yīng)用 SJA1000 的寄存器和管腳配置允許它使用于各種各樣的集成的或分立的 CAN 收發(fā)器這使不同微控制器之間的接口能夠被靈活運用 。 一個包括 80C51 微型控制器和 PCA82C250 收發(fā)器的典型 SJA1000 應(yīng)用圖如圖 3所示 CAN 控制器功能作為一個時鐘源復位信號由外部復位電路產(chǎn)生在這個例子里SJA1000的片選由微控制器的 P2.7口控制否則這個片選輸入必須接到 VSS也可以通過地址解碼控制例如當?shù)刂?/數(shù)據(jù)總線用于其他外圍器件。 圖 3 典型的 SJA1000應(yīng)用 3.2 電源 SJA1000有三組電源引腳用于 CAN控制器內(nèi)部不同的數(shù)字和模擬模塊 ： 1.VDD1/VSS1內(nèi)部邏輯數(shù)字。 2.V